simple IQ-Modulation with cordic(finished)
Reinhard
Posts: 489
Before I get the silicon (thanks to Connecticut)
I can think of a few more theoretical thought experiments.
How about an IQ modulator?
As you know, the equation is
f_sig_out = f_sig_in * cos (f_carrier) + f_sig_in * sin (f_carrier)
This means if an input signal is modulated without a DC component
a frequency spectrum is created with f_carrier + - f_sig_in.
With the DC component, f_carrier - f_sig_in, f_carrier, f_carrier + f_sig_in is created.
Only DC input, no AC, creates f_carrier.
I simulated exactly this case with the help of the Cordic solver.
One can do without the two multiplications if the
qrotate statement with which input is scaled.
I can think of a few more theoretical thought experiments.
How about an IQ modulator?
As you know, the equation is
f_sig_out = f_sig_in * cos (f_carrier) + f_sig_in * sin (f_carrier)
This means if an input signal is modulated without a DC component
a frequency spectrum is created with f_carrier + - f_sig_in.
With the DC component, f_carrier - f_sig_in, f_carrier, f_carrier + f_sig_in is created.
Only DC input, no AC, creates f_carrier.
I simulated exactly this case with the help of the Cordic solver.
One can do without the two multiplications if the
qrotate statement with which input is scaled.
dat
org 0
mov angle,#0
mov sig_in,#100 'DC constant
loop
mov sig_out,#0 'clear output
qrotate sig_in,angle
getqx x 'x = sig_in * cos(angle)
getqy y 'y = sig_in * sin(angle)
add sig_out,x
add sig_out,y 'sig_out = x + y
add angle,##$800_0000 'increment 11,25°
jmp #loop
x res 1
y res 1
angle res 1
sig_in res 1
sig_out res 1
Comments
I actually got the 1024-point FFT running in under 1ms, but I want to spend more time later making it work by self-modifying code, so that it takes way less space.
But I have no experience in compiler construction.
I am an electrical engineer, not a computer scientist.
I have some experience in assembler programming in my professional life,
(PIC's), lots of knowledge of C and math.
I would also like the P2 to be given more attention in Germany.
so if German speakers are present here, maybe we can do something
to launch ?
I can only say that I respect the 1024-FFT !
Reinhard
This is a big advantage over other DSPs.
I see a few limitations:
8 bit output
Q output only
output to DAC or digital pins? only
no way to reset phase (perhaps this could be worked around by running at a very low frequency and stopping it at a certain phase)
None of this matters for an RF modulator. Except maybe the 8 bits.
It only outputs to the DAC channels.
The only way to reset its phase is to disable and reenable it.
I logged the output of the simulation and entered a scilab script.
The result corresponds to the theory.
dat org 0 mov temp,#0 loop mov angle,temp 'this is for f_sig_in mov angle2,angle 'this is for f_carrier mul angle2,#20 'f_carrier = 20 * f_sig_in sal angle,#16 sal angle2,#16 qrotate #100,angle 'make sig_in mov sig_out,#0 'clear output getqx sig_in 'sig_in = cos(angle) qrotate sig_in,angle2 'perform iq modulation getqx x 'x = sig_in * cos(angle2) getqy y 'y = sig_in * sin(angle2) add sig_out,x add sig_out,y 'sig_out = x + y add temp,##$800 'increment (after sal 11,25°) jmp #loop x res 1 y res 1 angle res 1 angle2 res 1 sig_in res 1 sig_out res 1 temp res 1sig*sin(ct) + sig*cos(ct)
sig*( sin(ct) + cos(ct) )
sig*sqrt(2)*cos( ct - pi/4 )
Thanks, Chip.
That is still an improvement over the P1, which had no way to reset the chroma phase.
a) sig*sin(ct) + sig*cos(ct)
b) sig*( sin(ct) + cos(ct) )
c) sig*sqrt(2)*cos( ct - pi/4 )
Yes, it show the principe of double sideband modulation with suppressing carrier.
if we say sig = cos(phi) and ct = (20*phi)
we get sig_out = cos(phi) * cos(20*phi) + cos(phi) * sin(20*phi)
this is the a formula for double sideband modulation and corresponds with your equation a)
b) and c) are alternative forms.
Another alternative form is 0.5(sin(19*phi) + sin(21*phi) + cos(19*phi) + cos(21*phi))
Here ws see the sum and diffs in frequency domain, the carrier is suppressed.
If I get my ev board, I make a physical signal.
Reinhard
P.S. I am back in the forum after new year.
At the beginning of the 90's I was working in a company in germany. The CEO was an American. In the 1960s he acquired the monopoly of transmitting background music to shops and hotels via telephone lines, (muzak) .In the 1990s he terminated the lines and rented a transponder on a semi-commercial satellite. (Kopernikus3).
But the signal had to be encrypted. At that time, digital processing was not yet available cheaply. In the course of my thesis, I developed an analog scrambler. The band-limited audio signal was modulated up and down again.
The upper sideband is cut and what is left is a frequency shifted and sideband inverted audio spectrum. This process was reversed in the receivers and the plain signal was audible. An entire European board was required for the analog components. Now I want to do a retro development with a chip for fun. I think this is easy for P2.
Back to the thread:
For the first one, I connected an external 8-bit R2R DAC because I just have it in my handicrafts. I don't want to be able to output it on a smartpin yet. I'm probably doing something wrong. I copied templates from the P2 Audio Out thread, but the pin remains silent. It would be great if someone could help me with a code snippet.
const 'from forum thread P2 AUDIO OUT L_PIN = 0 R_PIN = 1 SYSTEM_CLOCK = 250000000 SAMPLE_RATE = 250000 INIT_8BIT_DAC_VALUE = 128 DAC_MODE = %00011_0 ' DAC 16-bit dither, PWM DIR_MODE = %01 ' Output enabled, overrides DIR ANALOG_OUT_MODE = %10111 ' 75 ohm, 2.0V DAC mode SMARTPIN_DAC_MODE = (ANALOG_OUT_MODE << 16) | (INIT_8BIT_DAC_VALUE << 8) | (DIR_MODE << 6) | DAC_MODE SAMPLE_PERIOD = SYSTEM_CLOCK / SAMPLE_RATE 'CPU cycles between sample updates dat org 0 hubset ##%1_000001_0000011000_1111_10_00 'config PLL, 20MHz/2*25*1 = 250MHz waitx ##20_000_000 / 200 'allow crystal+PLL 5ms to stabilize hubset ##%1_000001_0000011000_1111_10_11 'switch to PLL mov dira,#255 mov temp,#0 'from forum thread P2 AUDIO OUT 'wrpin SMARTPIN_DAC_MODE, #L_PIN ' Config smartpin DAC mode on "left" pin 'wrpin SMARTPIN_DAC_MODE, #R_PIN ' Config smartpin DAC mode on "right" pin 'wxpin SAMPLE_PERIOD, #L_PIN ' Set sample period for left audio channel 'wxpin SAMPLE_PERIOD, #R_PIN ' Set sample period for right audio channel 'dirh #L_PIN ' Enable smartpin DAC mode on left pin 'dirh #R_PIN ' Enable smartpin DAC mode on right pin 'setse1 #%001_000000 | L_PIN ' Event triggered every new sample period (when "left in pin rises") loop mov angle,temp 'this is for f_sig_in mov angle2,angle 'this is for f_carrier mul angle2,#20 'f_carrier = 20 * f_sig_in sal angle,#16 sal angle2,#16 qrotate #100,angle 'make sig_in mov sig_out,#0 'clear output getqx sig_in 'sig_in = cos(angle) qrotate sig_in,angle2 'perform iq modulation getqx x 'x = sig_in * cos(angle2) getqy y 'y = sig_in * sin(angle2) add sig_out,x add sig_out,y 'sig_out = x + y add temp,##$800 'increment (after sal 11,25°) '----------------------OUTPUT STAGE------------------------------------- ' ok with external dac 'mov temp2,#128 'interims output stage 'sub temp2,sig_out 'to 8 bit dac 'and temp2,#255 'before I learned more 'mov outa,temp2 'about audio smart pins drvnot #2 'speed indicator : 781.2 kHz ! 'from forum thread P2 AUDIO OUT wypin temp2, #L_PIN ' Output sample on left channel wypin temp2, #R_PIN ' Output sample on right channel waitse1 '----------------------------------------------------------------------- jmp #loop x res 1 y res 1 angle res 1 angle2 res 1 sig_in res 1 sig_out res 1 temp res 1 temp2 res 1something is comment out in the code, for debug reasons.The reason for use the old R2R dac is, because I haven't Experience with smartpin handling.
Today I receive my EV Board and I wanted to see a quick success. Connect Osci to the pin and look at the signal.
But I don't see anything with the output to smartpin. The pin is at 0Volt. Or do I still need a resistor on the pin?
wrpin smartConfigAudioDAC, #L_PINsmartConfigAudioDAC from the snippets of thread P2 Audio Out was not defined.
I thought that's ok,but maybe not.
wrpin SMARTPIN_DAC_MODE, #L_PINThe DAC output is what I want for first and what I expected.
A Happy And Succesfull New Year To All The Listeners!
Muzak, long long time ago.
I was from 1991 to 1993 in the company.
In Germany/Austria the was called funktionelle musik gmbh.
It was an exciting and interesting time.
Happy New Year.
I trimmed the sig_in frequency to 1kHz, the local oscillator frq. to 20kHz.
The sig_out has 19 and 21 kHz frequncy components.
the time domain looks: