Only one PLL?

ManAtWork · 2019-12-16 12:34

Have I missed something or is there really only one PLL for the system clock in the P2? I sometimes found it useful to have a seperate PLL in each cog to output an arbitrary frequency at any pin. Probably nobody is still doing analogue radio FM theese days but, for exmple, I used this to generate 24.576MHz for an external audio ADC.

Well, for a single fixed frequency you could always adjust the system clock so that the frequency to be generated is evenly divisible from the system clock. If jitter doesn't matter you could also use the NCO mode of smart pins. But for sigma/delta ADCs jitter has to be avoided as it would generate noise.

What happens to all those HF hacks (capacitive sensors, metal detectors...) that were so cool on the P1?

JRoark · 2019-12-16 12:51

There is only one PLL generating a system-wide clock in the P1, and each of the cogs runs at the same speed as every other. Thus the clock speed is universal throughout the chip. The P2 retained this concept. Is it possible you are thinking of another chip? Or have I misunderstood your question?

Edit: perhaps you may be thinking of the PLL’s/counter/timers on the output side of each cog?

Peter Jakacki · 2019-12-16 13:02

Each pin is a counter/timer/adc/dac/serial etc so you can output 64 different frequencies if you so desire. The "PLL" though is part of the chip-wide system clock.

Cluso99 · 2019-12-16 13:04

@JRoark
There are extra PLLs in the P1 and they are tied to the counters and video generation in each cog. It’s been a while so I suggest you look at the counter specs for full details. These are different to the PLL in the clock generator.

ManAtWork · 2019-12-16 13:29

JRoark wrote: »

There is only one PLL generating a system-wide clock in the P1, and each of the cogs runs at the same speed as every other.

Yes of course. Thank god we only have one system clock. As I already said elsewhere I hate those ARM µCs where peripherals can be clocked by a seperate clock and thus each register R/W has to be synchronised. And those damn prescalers. All completely unnecessary and a WOMBAT. I agree totally.

Peter Jakacki wrote: »

Each pin is a counter/timer/adc/dac/serial etc so you can output 64 different frequencies if you so desire.

Err, yes and no. If I understood correctly you can program the streamer or a smart pin to output any frequency but only in average. The NCO idea can produce fractional parts of the system clock frequency but only with jitter (spread spectrum) if the frequency divide ratio is not a whole number.

Only a true PLL can output an arbitrary frequency with narrow spectrum (almost no jitter). Some HF applications don't work with a wide spectrum such as FM radio. It would be awfully noisy with an NCO frequency generator.

Some of this would be better with DDS. But low SNR would require the generated wave to have a much lower frequency than the system clock. I guess this won't work well at 100MHz.

Not a big problem for me at the moment. My audio ADC also runs at 25MHz instead of 24.576. And in the case I need the exact sampling ratio I could adjust the crystal. I only wondered that some hacks are possible only with the P1 and not the P2.

Peter Jakacki · 2019-12-16 14:34

Each pin can indeed output a different frequency.
In TAQOZ I can type:
62 FOR I PIN I 1+ KHZ NEXT
and instantly it will output 62 different frequencies from 1kHz to 62kHz on P0..P61

My P2D2 includes a Si5351 clock gen chip with a 25MHz (or 26MHz GPS crystal) that is programmed at boot to output the P2 EVAL standard of 20MHz, but can be programmed for any frequency up to 200MHz as well as its two auxiliary clock outputs. But I believe the P2 RevB PLL works really well.

evanh · 2019-12-16 15:33

ManAtWork wrote: »

Err, yes and no. If I understood correctly you can program the streamer or a smart pin to output any frequency but only in average. The NCO idea can produce fractional parts of the system clock frequency but only with jitter (spread spectrum) if the frequency divide ratio is not a whole number.

Yes, this shows up in video displays as a shimmer in the picture. So we've got into the habit of always using whole divisors of the sys-clock.

Only a true PLL can output an arbitrary frequency with narrow spectrum (almost no jitter). Some HF applications don't work with a wide spectrum such as FM radio. It would be awfully noisy with an NCO frequency generator.

Not that I have any experience but I remember someone posting that the prop1 counter PLLs were a little noisy anyway. Not well suited to clean RF operation.

Phil Pilgrim (PhiPi) · 2019-12-16 17:59

The PLLs in the P1's counter/timers do exhibit phase noise, whose severity is a function of the freqx value in the driving NCO. A longer filter constant in the PLL's phase detector would have helped to reduce the noise, but it would have been at the expense of reaction time to a changing input frequency.

-Phil

jmg · 2019-12-16 20:12

ManAtWork wrote: »

Only a true PLL can output an arbitrary frequency with narrow spectrum (almost no jitter). Some HF applications don't work with a wide spectrum such as FM radio. It would be awfully noisy with an NCO frequency generator.

The P2 PLL is integer only, within these limits
%DDDDDD 0..63 1..64 division of XI pin frequency
%MMMMMMMMMM 0..1023 1..1024 division of VCO frequency

ManAtWork wrote: »

Not a big problem for me at the moment. My audio ADC also runs at 25MHz instead of 24.576. And in the case I need the exact sampling ratio I could adjust the crystal. I only wondered that some hacks are possible only with the P1 and not the P2.

Even 24.576 from P1 has noise, and Audio customers are going to want to see highest end specs. (best ppm and lowest jitter, as they will swear they can hear the difference

)

Best for Audio use will be a (vc)TCXO connected directly to the P2. A VCTCXO can be post assembly trimmed using a GPS calibrate./

If you are quick, Arrow have 90 of these VCTCXO on sale at just 50c (3225 package)
MMD Components I738-2P3-24.576 MHZ Oscillator VC-TCXO 24.576MHz ±1ppm (Tol) ±2ppm (Stability) 15pF HCMOS 60% 3.3V 4-Pin CSMD T/R
Arrow Electronics I738-2P3-24.576 MHZ 90 1 Cut Tape USD 0.500

If you want something even better, there is
XTCLH24M576THJA6P0 (VCTCXO) 24.576MHz ±0.2ppm 8-Pin 5032 SMD T/R $7.88/20+

or this
SIT5001AIC2E-33VQ-24.576000X Mems Osc Vctcxo 24.5760MHz ±5 ppm $5.14/10

Addit:
cheapest low jitter one, looks to be this
https://datasheet.lcsc.com/szlcsc/SHENZHEN-CRYSTAL-TECH-3N24-576G33YC_C252340.pdf 0.5ps Typ jitter, 100+ $0.38

and for more MHz (to allow bypass of P2 PLL jitter ) in larger $ and size, ABLNO-V-122.880MHZ (24.576*5 )
another option for 122.88MHz
AK5DAF1-122.8800T2 $3.68/10+, 70fs jitter, and ±25 ppm over -40°C to +85°C (LVDS, so termination tune would be needed to drive XI ?)

Or 122.88MHz with Trim
NDK NV7050SF-122.88M-NSA3527A Xtal Osc Vcxo 122.8800MHZ Cmos
Digi-Key3 644-1292-1-ND 74 1 Cut Tape USD 3.36 3.20 $3.04/100
NDK also have
NZ2520SDA (Ultra Low Phase Noise Type) Features Ultra low phase noise make this product ideal for High quality audio
Compact and light. Dimensions : 2.5 × 2.0 × 0.9 mm, weight : 0.02 g. Wide frequency range: 20 to 50 MHz.
Ultra low phase jitter (Typ. 43fs (Frequency Offset：12kHz to 20MHz)@49.152MHz, 3.3V)

ManAtWork · 2019-12-17 08:13

BTW, I don't process real audio signals but use the audio ADC to read a resolver. Here, only linearity of amplitude matters and not the exact frequency. Even gain and offset errors don't matter as long as both channels match. For this reason the audio ADC makes an excellent and very cheap (<$1) analogue front end for resolvers. Dedicated ICs designed for resolvers usually cost >$40.

jmg · 2019-12-17 09:38

ManAtWork wrote: »

BTW, I don't process real audio signals but use the audio ADC to read a resolver. Here, only linearity of amplitude matters and not the exact frequency. Even gain and offset errors don't matter as long as both channels match. For this reason the audio ADC makes an excellent and very cheap (<$1) analogue front end for resolvers. Dedicated ICs designed for resolvers usually cost >$40.

Ah, ok, if you do not have to play with other Audio systems at all, then almost any ballpark MHz will do.

There will be P2 users who do want to interface to other audio systems, so they would need the better 24.576MHz (or multiples) spec oscillators.
122.88MHz does seem a common higher MHz integer multiple, for those wanting to avoid P2 PLL, or use highest PFD.

SaucySoliton · 2019-12-17 19:05

ManAtWork wrote: »

Err, yes and no. If I understood correctly you can program the streamer or a smart pin to output any frequency but only in average. The NCO idea can produce fractional parts of the system clock frequency but only with jitter (spread spectrum) if the frequency divide ratio is not a whole number.

Only a true PLL can output an arbitrary frequency with narrow spectrum (almost no jitter). Some HF applications don't work with a wide spectrum such as FM radio. It would be awfully noisy with an NCO frequency generator.

Some of this would be better with DDS. But low SNR would require the generated wave to have a much lower frequency than the system clock. I guess this won't work well at 100MHz.

Not a big problem for me at the moment. My audio ADC also runs at 25MHz instead of 24.576. And in the case I need the exact sampling ratio I could adjust the crystal. I only wondered that some hacks are possible only with the P1 and not the P2.

Because of the P2's much higher sysclock, the NCO output should be of similar quality to the P1 even with no PLL to filter it. The propeller PLLs don't filter much noise anyway.

DDS will work at 100MHz. But you will need a lowpass or bandpass filter to clean the output. (In Nyquist we trust

) The RF sensing hacks for P1 would use the Goertzel mode on the P2. Likely with far better results.

Another option would be to adjust the P2 PLL to a multiple of 24.576. I haven't checked to see if that is exactly possible. But since the exact sampling frequency doesn't matter I think you are on the right approach of minimizing jitter.

Only one PLL?

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