Need help with DAC / streamer configuration
ozpropdev
Posts: 2,793
in Propeller 2
Hi All
I'm converting some old FPGA code to real silicon.
I had a 4 bit R2R ladder on pins 11..8 on the FPGA which I streamed data to.
This works great!
I now want to switch to internal pin DAC.
I'm not having much luck.
Need someone with fresh eyes to find my mistake.
I'm converting some old FPGA code to real silicon.
I had a 4 bit R2R ladder on pins 11..8 on the FPGA which I streamed data to.
This works great!
I now want to switch to internal pin DAC.
I'm not having much luck.
Need someone with fresh eyes to find my mistake.
con
use_dac = true 'false = r2r,true = pin dac
xtal = 12_000_000
dv = xtal / 1_000_000,mlt = 80 '80MHz
sys_clk = xtal / dv * mlt
clk = 1 << 24 | (dv-1) << 18 | (mlt-1) << 8
dat org
hubset ##clk | %1111_01_00
waitx ##20_000_000/100
hubset ##clk | %1111_01_11 '80mhz clock
qfrac ##10_000,##sys_clk << 1
getqx pa
setxfrq pa 'set streamer freq to 10kHz
mov pa,##use_dac wz
if_z setnib dira,#$f,#2 '4 bit r2r ladder P11..P8
if_nz wrpin ##%10100_000000000_01_00000_0,#8 'DAC mode
if_nz dirh #8
loop getct pa
addct1 pa,##sys_clk / 2
waitct1
rdfast #0,##$400
if_z mov pa,streamer_r2r
if_nz mov pa,streamer_dac
add pa,##sample_end-sample
xcont pa,#%00110
jmp #loop
streamer_r2r long %0001_0000_1001_0000 << 16 'rfbyte 4 bit reorder ,pins 39..8
streamer_dac long %0001_0001_0000_0000 << 16 'rfbyte 4 bit reorder , output X0 on all four DAC channels
orgh $400
sample file "ufo_killed_sound.dat"
sample_end
Comments
XCONT {#}D,{#}S Buffer new streamer command to be issued on final NCO rollover of current command, continuing phase.
dat org hubset #%1000 waitx ##20_000_000/100 hubset #%1010 wrpin ##%10110_00000000_01_00000_0,#0 'DAC mode dirh #0 rdfast #1,##sample setxfrq ##$8000_0000 xcont streamer_dac,#%00010 jmp #$ streamer_dac long %0001_0001_0000_0000 << 16 + $FFFF 'rfbyte 4 bit reorder , output X0 on all four DAC channels orgh $400 sample long $76543210,$FEDCBA98 long $76543210,$FEDCBA98 long $76543210,$FEDCBA98 long $76543210,$FEDCBA98 long $76543210,$FEDCBA98 long $76543210,$FEDCBA98 long $76543210,$FEDCBA98 long $76543210,$FEDCBA98You had 9 zeroes in your DAC-value field, where you should have had 8.
Something seems strange, though, because every other output update, the top nibble of the DAC value seems to go to %0000.
That fixed it.
I see what you mean about the alternate nibbles.
I've got the pin and DAC data tangled up. They need to be separate.
That's better
Absolutely. I've been looking and looking at the related Verilog and I know what signal is causing the problem, but not how it's causing it.
I switched back to streaming direct to the pins and the data doesn't appear to exhibit the alternate 0000's issue, if that helps.
Yes, it just happens to the DAC data when the pins are disabled by bit7 being low. So, for now, if you want to stream to the DAC, you'll have to enable the pins (bit7 high), but park them somewhere you're not using pins, and then keep their DIRs low.
The "PAD_IO Modes" sheet has two tables. The left hand table I think I've got a handle on, but the right hand table I've really struggled to work out where it fits in.
The right hand table breaks down as follows:
Column "CIOHHHLLL" shows what bits are flexible and which are held in fast states for all the modes.
Column "OE" shows what signal controls the digital output enable. It's always DIR, except in the case of the DAC modes, where it's 0 (off).
Column "DAC" shows when the DAC output is enabled. It's only on when in DAC mode and DIR is high.
Column "ADC" shows when the ADC is enabled. In DAC modes, OUT enables ADC (DIR must be high, too).
Column "ADC Mode" shows the ADC mode settings for ADC and DAC modes. For DAC modes, it's fixed at %011 which is "PinA 1x".
Column "Comp" shows what modes the comparator is enabled in and what its inputs are.
This table was made for my own use in the schematic software where the I/O pin was designed.
Yes.
Right. PinA is that very pin. PinB is its even/odd neighbor.
I'm curious why PeterJ's VGA code does not seem to have this effect - is that Streamer-LUT-DAC use a different-enough pin mode to miss this issue ?
It only happens on 4/2/1- bit DAC output modes.
WRPIN ##%101xx_0000cccc_01_00000_0, #dacpin 'select cog %cccc's DAC channelsWhere %cccc = cog from which DAC data is coming.Doh, of course, PinA can be either even or odd.
Yah, that's difficult to document in a clean fashion. It triggers on that combination of %101 dac mode and %01 pin source.
PS: I wonder what will happen if used in the smartpin DAC modes, as in
WRPIN ##%101xx_0000cccc_01_00010_0, #dacpin 'select cog %cccc's DAC channelsEDIT: Sorted, that is output enable control for all smartpin modes.
I think its purpose is to make OUT toggle the output between two DAC levels. This is the mode I think Chip was mulling over changing its behaviour ...
As it is, a high will be whatever you set the 8-bit DAC value to and a low will be $00.
WRPIN ##%101xxDDDDDDDD_1x_00000_0, #tpin%DDDDDDDD sets the DAC level. 101xx is the usual DAC modes. The _1x_00000_0 tells it to be BIT_DAC operated.Look right?
Got it! It sunk in finally. The columns with fixed digits are not in the instruction encodings as individual bits. They're inherent in the mode. Eg: I can see the 1k5 resistor selected in all the DAC comparator modes.