P2 Boot Decision Tree Suggestions

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  • dMajodMajo Posts: 827
    edited 2016-09-27 - 16:58:36
    jmg wrote: »
    cgracey wrote: »
    Going beyond three wires means going to six wires and issuing all the 'exit-QPI' commands and then all the 'reset' commands you can learn about. Or, after all the 'exit-QPI' commands, wait out any erase or program that is in-progress.
    I'm really not following this ? - you can issue EXIT QPI commands even in 3-pin mode, to the majority of P2-target parts.
    The next step after 3-Pin mode, is 4 pin, as shown in #1.

    It is actually very easy to test and confirm - Just add some RESET preambles to your 3-bit code, and release to users.

    User can place various parts into Quad mode, using that 3 Pin connection, and then try Reboot, and report back.
    There is always Power Cycle recovery during these tests.
    cgracey wrote: »
    Of course, there's the reset input that exists on some SPI flash chips that would be much better to use.

    See above, on the Winbond data I have here, the combined Hold/Reset pin does not work, in Quad mode....

    A Higher pin count package (SO16N, or BGA)** does have a separate reset pin.
    To use that separate pin, (no longer shared) you have increased the pin impact to users wanting Software reboot.

    It is probably tolerable to those using external watchdogs, as they connect watchdog to P2.RESET and SO16N.RESET
    cgracey wrote: »
    Three-wire is the most sure-fire approach and it reduces the pin ghetto. Going beyond three pins is a huge step.

    ? The next step above 3 pin, is 4 pin ?


    ** just checked Digikey, who have 2,939 entries under Serial Flash.
    For SO16N, they list just 1 part, (N25Q032A11ESF40G-ND) not stocked, no price given.
    For wide body SO16W, they list 452 parts, price starts at 40c/3k (no stock) for 32MBit
    For stocks > 100 pcs, price is 64c/3k.
    (compare with sub 15c/3k start for SO8 mainstream standard package)

    You all are confusing QPI with SQI

    Standard SPI (or SPI), Dual SPI (or SDI) and Quad SPI (SQI) all uses 1b communication for commands and 4b comunication for data exchange. That means 8 clocks to transmit command and 2 clocks then to transfer a byte (parameter)

    QPI, when enabled, switches ALL the communication to 4b. That means 2 clocks for command and then 2 clocks for each byte. When into this mode, to exit it you need the exit command being transmitted in 4b.

    Chip is right for exit QPI on some parts you need to drive all 4 IO signals.


    Jmg, the reset (on shared pin) is disabled only in QPI (full 4b mode) while it is functional in SPI, SDI and SQI. Always for the former two, only with CS deasserted with the later.
    The separate/dedicated reset on 16 pin devices is working always.
    Power-cycling, sw_resetting (or hw_resetting where a dedicated pin is present) the device while it is in the QPI will revert it back to SPI even if the non-volatile QPI_Enable will remain set and hold/reset shared functionality disabled. For QPI you must infact first enable(allow) it through the non-volatile register (which disables shared functions). Then you can activate it with a 1b command and deactivate(exit) it with a 4b command. The register value can be toggled only in 1b mode.
    So to exit the QPI and not complicate the boot the easiest way is to reset the device with its dedicated pin. This will put the device into SPI mode even if the non-volatile register will still remain set. That means that to activate again QPI is enough to issue the command without bother with register toggling.

    If the reset pulse is provided on IO3, which will in turn reset all SPI/SDI/SQI modes but not QPI (because the shared functionality is disabled), it is then very easy, with two external gates, drive the dedicated reset pin on 16 pin device from CS and IO3(Reset) signals.



    So with 4 wire setup and reset pulse you can:
    - with any flasy: boot in SPI and remain in SPI
    - with flash having shared reset: boot in SPI and then use it in SPI/SDI/SQI
    - with 16pin flash and 2 gates: boot in SPI and then switch to SDI/SQI and even QPI

    If only SPI is required (from the user-code) apart from the single pulse during boot the IO3 remains free. There are many things this pin can do (eg driving leds) for which the pulse is not dangerous. Otherwise some kind of SPIonly setup/configuration/detection during boot can avoid the pulse.
  • Ariba wrote: »
    cgracey wrote: »
    ...

    Here is a fact, as I see it: If you are going to have discrete DI and DO connections, but don't intend to use a 4-bit data path (DQ3..DQ0), you might as well tie DI and DO together and have a single data pin to the Prop2, as there is going to be no significant performance difference (only making the data signal an input before the 8th clock on commands which return data). Given that, the next step up is to wire for DQ3..DQ0 and go through the whole set of exit-QPI and reset commands, so that the flash can be booted from in DI/DO SPI mode. Am I wrong on any of this?

    You forget the DualRead Modes. With 4 pin SPI connection (DI, DO not tied together) you can read data two times as fast as in 1bit SPI mode.
    I've done that on FPGA Developmentboards which normally have no Quad compatible connection of the Config-Flash, but Dual mode works always. If you want to execute code from the Flash the double rate helps alot.
    The Dual modes also have no sticky variants, they always terminate when /CS goes high.

    Andy

    Ah, yes. I didn't think about that. Thanks for bringing that up.

    So, we could have 3-, 4-, or 6-pin hookups. The 6-pin, on boot, may only be to ensure that WP and HOLD are held high.
  • jmgjmg Posts: 14,567
    Ariba wrote: »
    You forget the DualRead Modes. With 4 pin SPI connection (DI, DO not tied together) you can read data two times as fast as in 1bit SPI mode.
    I've done that on FPGA Developmentboards which normally have no Quad compatible connection of the Config-Flash, but Dual mode works always. If you want to execute code from the Flash the double rate helps alot.
    Good point, my tree has this covered.
    Ariba wrote: »
    The Dual modes also have no sticky variants, they always terminate when /CS goes high.
    Seems a sweeping claim ?
    Given many data sheets I have mention explicitly a Dual-Exit command, I will keep that in the preamble.
  • jmgjmg Posts: 14,567
    cgracey wrote: »
    So, we could have 3-, 4-, or 6-pin hookups. The 6-pin, on boot, may only be to ensure that WP and HOLD are held high.
    Yes.
    Rayman wrote: »
    Actually, check out this page on how NXP deals with SQI flash:

    http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/lpc-cortex-m-mcus/lpc-cortex-m3/lpc1800-cortex-m3/lpc-spifi-peripheral:SPIFI-NXP-MICROCONTROLLERS

    Basically, they require that flash reverts to SQI mode on receipt of 0xFF command.
    Also requires read command on 0x03.

    There is a list of several vendors who support this.

    Anyway, here is a clear example of how to solve this problem.

    Nice find, exactly what I have been saying : Provide a reset preamble(s), and list vendors.

    I will observe NXP have missed Dual-Exit preamble, and likely pre-date the newer 0x66,0x99 string I have included.
  • jmgjmg Posts: 14,567
    edited 2016-09-27 - 18:50:29
    dMajo wrote: »
    You all are confusing QPI with SQI
    Nope, I just read the data sheets, and apply the rules therein.
    QPI and SQI are not universal semantics, if I search data, sometimes I find neither.
    If vendors do not use the terms, then neither do I.
    dMajo wrote: »
    QPI, when enabled, switches ALL the communication to 4b. That means 2 clocks for command and then 2 clocks for each byte. When into this mode, to exit it you need the exit command being transmitted in 4b.
    Almost right, again, you read too much into semantics that are not standard.
    If you look carefully, the exit command used in 4b mode, actually pivots on bit M4, which arrives on SIO0, so that command can be sent on a 1-wire system.
    That is why they chose that bit.
    dMajo wrote: »
    Chip is right for exit QPI on some parts you need to drive all 4 IO signals.
    I have yet to find a part that cannot exit using M4-bit, but there may be a fringe few...
    dMajo wrote: »
    Jmg, the reset (on shared pin) is disabled only in QPI (full 4b mode) while it is functional in SPI, SDI and SQI. Always for the former two, only with CS deasserted with the later.

    I can find many parts, that explicitly state, in their Quad Modes, that RESET pin is disabled.
    My parts are listed in first 2 posts.

    dMajo wrote: »
    If the reset pulse is provided on IO3, which will in turn reset all SPI/SDI/SQI modes but not QPI (because the shared functionality is disabled), it is then very easy, with two external gates, drive the dedicated reset pin on 16 pin device from CS and IO3(Reset) signals.

    As before, I am fine with adding a reset pulse, but pin-reset can be disabled on the parts in my list.
    ie do not expect this to work alone. Given the preambles DO work, to me, a reset pin is less vital.
    I warn many will not like the idea of an Active pulse out, on an unused pin, so any pulse would be only in 6-pin mode.

    The trend seems to be to have 0x66,0x99 (which is always issued as a 1-bit command) as the reset, given the shared pin can be disabled.
  • jmg wrote: »
    Nice find, exactly what I have been saying : Provide a reset preamble(s), and list vendors.

    I will observe NXP have missed Dual-Exit preamble, and likely pre-date the newer 0x66,0x99 string I have included.

    I'm not sure it's worth including 0x66,0x99 support just for one device...
    If you look at all the Winbond parts listed here:
    http://www.winbond.com/export/sites/winbond/product/files/SerialFlashProductSelectionGuide021116.pdf

    All the W25Q parts are supported, the vast majority.
    It is a shame that the highest density part, W25M512JV, doesn't support it.
    But, that's a strange bird anyway. Looking at the datasheet it's actually two 256M-bit chips in one package. Has some other strange commands to let you pick which chip to talk to...


  • jmgjmg Posts: 14,567
    Rayman wrote: »
    I'm not sure it's worth including 0x66,0x99 support just for one device...
    ??
    The cost of including it, is surely trivial. (IIRC Peter has tested this is simply ignored on older parts)

    The cost of excluding it, is much more serious as it seems Winbond and Macronix (at least) are using 0x66,0x99 on newer parts. That means more will add this in future.

    To me, they stipulate strict CS rules on this adjacent command, which means it can work no matter what else other parts of the device is doing.
    I think that is why they added this, plus it does more than just exit-quad.
    Note this command also has a post-command delay associated with it. See my other posts.


  • If you look at that table, many of the W25Q devices are brand new too.

    That W25M just has a lot of weirdness to it...
  • Ok, seems I'm wrong about "all W25Q" just needing $FF. That must have been old info.

    Looking at this datasheet, I see what jmg is talking about:
    713 x 453 - 17K
  • RaymanRayman Posts: 11,682
    edited 2016-09-27 - 21:54:22
    Actually, $FF alone may work for the W25Q128FV figure shown in last post...

    Only caveat there is to only use QPI mode and not SQI mode.
    QPI looks superior anyway.

    If the device is in QPI mode, $FF sends it back to SPI mode.

    Still, adding in the $66, $99 sequence after that in 1-bit SPI mode looks like good idea too.
    Actually, I'm still not sure if we need the $66, $99....
  • jmgjmg Posts: 14,567
    Rayman wrote: »
    Still, adding in the $66, $99 sequence after that in 1-bit SPI mode looks like good idea too.

    Agreed. It does need a delay, post-issue, as this is a 'bigger hammer'.

    Macronix data specifically says this re $66,$99 : The SIO[3:1] are "don't care".
    They do not have M4, but instead confusingly renamed it P4, and I think this does have the $ff exit

    They say
    "Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF"
    ie, P4=P0 is SDI0 pin only, and 'OR' above makes other pins "don't care"
  • Ok, I think I get it now after reading a Winbond datasheet...

    What they call QPI is what everyone else calls SQI.
    But, they also allow quad I/O data transfers while in SPI mode via special commands.

    All we need to do is get out of QPI mode.
    This just takes $FF.
  • Jmg, do you have a comprehensive list of commands that can be issued to reset most flashes? And are they all SPI, or are some QPI/SQI? I think I've made peace with all this.
  • jmgjmg Posts: 14,567
    edited 2016-09-28 - 01:56:07
    cgracey wrote: »
    Jmg, do you have a comprehensive list of commands that can be issued to reset most flashes? And are they all SPI, or are some QPI/SQI? I think I've made peace with all this.

    See #1

    I'd start with $ff, which NXP also use, and include the closely related $ffff, as that allows Dual-IO, which is the no-added-pins but 2x bandwidth coverage.

    Check with Cluso on how many clocks are needed to release SD cards, and add that when CS=H (16?,24?,?)

    There is also the more formal reset $66,$99 - those are a bigger hammer, and need a delay post-issue.
    Many parts suggest 30-35us, but Macronix MX25R1635F expands this to vary by operation.
    I see they also say "It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence."

    You have mentioned polling before, to check erase etc are done, so most flexible may be to poll before $ff/$ffff, to confirm not busy, then the formal reset has a more defined delay.

    An initial test build with a simple $ff,$ffff, $66,$99 and 40us delay, would let field testing start.
    Those are all 1-pin, single SPI commands with 8,16,8,8, clocks respectively per CS frame.

  • Looks to me like "exit sqi" as $FF is all we need. Also, it looks like has to be in 4-bit mode:

    So, could work with some external pullup resistors.
  • jmgjmg Posts: 14,567
    edited 2016-09-28 - 02:32:17
    Rayman wrote: »
    Looks to me like "exit sqi" as $FF is all we need. Also, it looks like has to be in 4-bit mode:

    That 4-bit mode command, is not valid for all vendors parts, (but feel free to include it in the list), and Winbond 25Q128FV data also says this , which covers the M4 exit mode I have mentioned above:

    "If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the E3h instruction code, as shown in Figure 27b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low....
    It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation."



  • Okay. Would anyone mind coming up with a complete sequence, so we could all get on the same page? We should be able to agree on the order, width, and length of a string of commands to pull any SPI's head out of its cloud.
  • jmgjmg Posts: 14,567
    edited 2016-09-28 - 03:41:08
    cgracey wrote: »
    Okay. Would anyone mind coming up with a complete sequence, so we could all get on the same page? We should be able to agree on the order, width, and length of a string of commands to pull any SPI's head out of its cloud.

    Yup, I've expanded #1, with this minimum preamble
    Suggested preambles, 
    Function Send_1b_CS (NClocks, DataLJ)            ' sends N clocks, Data on DIO0, with std CS frame  =\__/==
    
    Send_1b_CS(8,$ff)         ' classic M4 exit Quad command, as in NXP etc
    Send_1b_CS(16,$ffff)     ' classic M4 exit Dual command
    Send_1b_CS(2,$ff)         ' nibble coverage, in case any parts lack the above, assumes Pullups on DIO3..DIO0.
    ' <<  by here, BUS should be back in Single-bit mode.
    PollBusy                        ' confirm device connected, and confirm is not Busy
    
    ' Boot here, or do a hard reset ?
    
    
    Pullups on all pins, would allow field testing & gives HOLD#,WP# = Hi
  • Thanks, jmg.

    Now, what would you add to get better coverage (ie $66, $99)?
  • RaymanRayman Posts: 11,682
    edited 2016-09-28 - 13:28:56
    I guess you could try your single pin DO/DI first.
    Maybe this would be a failsafe.
    Would also allow you to conserve pins, in case that is needed.

    Then, work with the 4-pin mode...
  • Rayman wrote: »
    Ok, seems I'm wrong about "all W25Q" just needing $FF. That must have been old info.

    Looking at this datasheet, I see what jmg is talking about:

    Yes, 66+99 is sw reset, identical to hw_reset where a shared or dedicated pin is present.
    sw_reset have to issued with 2 consecutive commands with a CS toggle between them. Reset is initiated when CS goes high after the second command.
    In SPI/SDI/SQI the sw_reset must be issued in 1bit format while in QPI the sw_reset must use 4bit format
  • dMajodMajo Posts: 827
    edited 2016-09-28 - 11:16:27
    Rayman wrote: »
    Actually, $FF alone may work for the W25Q128FV figure shown in last post...

    Only caveat there is to only use QPI mode and not SQI mode.
    QPI looks superior anyway.

    If the device is in QPI mode, $FF sends it back to SPI mode.

    Still, adding in the $66, $99 sequence after that in 1-bit SPI mode looks like good idea too.
    Actually, I'm still not sure if we need the $66, $99....

    Yes, FF brings the device in SPI again. But if you issue it in SPI while the device is in QPI you need to drive high /pull-up IO1,IO2,IO3 while issuing command.

    But while issuing a "FF" will change mode, the 66+99 is sw_reset. the Reset will immediately end any pending process (erase, programming, ...) inside the flash device. It's the same as power-cycle it. After the 66+99 sequence you fave to wait for device internal initialization prior to start communicating with it again.
  • dMajodMajo Posts: 827
    edited 2016-09-28 - 11:36:41
    jmg wrote: »
    cgracey wrote: »
    Jmg, do you have a comprehensive list of commands that can be issued to reset most flashes? And are they all SPI, or are some QPI/SQI? I think I've made peace with all this.

    See #1

    I'd start with $ff, which NXP also use, and include the closely related $ffff, as that allows Dual-IO, which is the no-added-pins but 2x bandwidth coverage.

    Check with Cluso on how many clocks are needed to release SD cards, and add that when CS=H (16?,24?,?)

    There is also the more formal reset $66,$99 - those are a bigger hammer, and need a delay post-issue.
    Many parts suggest 30-35us, but Macronix MX25R1635F expands this to vary by operation.
    I see they also say "It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence."

    You have mentioned polling before, to check erase etc are done, so most flexible may be to poll before $ff/$ffff, to confirm not busy, then the formal reset has a more defined delay.

    An initial test build with a simple $ff,$ffff, $66,$99 and 40us delay, would let field testing start.
    Those are all 1-pin, single SPI commands with 8,16,8,8, clocks respectively per CS frame.

    I will first start just by only driving CLK with a given number of pulses to release an eventual SD. This anyway, prior to any test for SD/Flash or whatever boot device

    Then, in case of flash boot,
    - I will issue a "partial" "FF": two ones in a CS frame of two clocks. If user is using devices in QPI he can provide 3 weak pull-ups on IO1, IO2 and IO3 to complete the two nibbles for the entire "FF" value. This will eventually bring the part out of QPI. If it is not in QPI then the CS going high after 2 clocks will abort and prepare the internal logic for the next comand in SPI so you know that further commands sequence will work.
    - Then you go with the Jmg sequence $ff,$ffff, $66,$99 and 40us
  • RaymanRayman Posts: 11,682
    edited 2016-09-28 - 13:19:02
    I'm on the fence with the $66, $99. NXP decided just to give a $FF in 4-pin mode and that's it.

    So, what if flash was in process of being written to when P2 got reset?
    Maybe the $66,$99 would help.
    Or, maybe the ms of time the P2 spends first trying serial is so long that it's not needed...
    There must be some internal timeout...
  • In the datasheet they advise that any pending transaction will be interrupted by reset thus the possibility of data loss.
    So some suggests testing for busy prior to issuing reset. But testing for busy suppose communicating with the right mode which the flash is currently in.
  • NXP just requires that all devices accept $FF in 4-pin mode to exit and return to 1-pin mode.
    The only other thing required it to have the same read command.
  • Rayman wrote: »
    NXP just requires that all devices accept $FF in 4-pin mode to exit and return to 1-pin mode.
    The only other thing required it to have the same read command.
    One potential problem is that you're looking at an NXP part that is already on the market but we're talking about a chip that will likely take another year to reach production.

  • Well, their SPIFI library was beta in 2014. So, I think it is a fairly recent solution...
  • dMajodMajo Posts: 827
    edited 2016-09-28 - 17:31:31
    Rayman wrote: »
    NXP just requires that all devices accept $FF in 4-pin mode to exit and return to 1-pin mode.
    The only other thing required it to have the same read command.
    They say
    Any device that can accept a 03 read serial opcode after receiving an FF opcode is expected to boot successfully.
    A device that switches to quad opcodes and doesn't return after an 0xff reset to serial mode might not boot after a reset.

    So I think they expect to exit SQI issuing "FF" in SPI, I mean using 1b command. This expectation is wrong in case of QPI. Nothing wrong in this, they simply not support this kind of devices.
  • dMajo wrote: »
    Rayman wrote: »
    NXP just requires that all devices accept $FF in 4-pin mode to exit and return to 1-pin mode.
    The only other thing required it to have the same read command.
    They say
    Any device that can accept a 03 read serial opcode after receiving an FF opcode is expected to boot successfully.
    A device that switches to quad opcodes and doesn't return after an 0xff reset to serial mode might not boot after a reset.

    So I think they expect to exit SQI issuing "FF" in SPI, I mean using 1b command. This expectation is wrong in case of QPI. Nothing wrong in this, they simply not support this kind of devices.
    That is probably a good compromise for P2 as well. We support SQI but not QPI.

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