P2 smart pins just DAC but no ADC?
msrobots
Posts: 3,704
in Propeller 2
Going thru the Google docs documentation I find no reference to ADC.
64 analog pins implied to me that not just DAC (as in analog output) is possible but also ADC (as in analog input).
Am I completely wrong here or did ADC got cancelled? I think that analog input (and streaming to HUB/LUT) would be very useful.
confused,
Mike
64 analog pins implied to me that not just DAC (as in analog output) is possible but also ADC (as in analog input).
Am I completely wrong here or did ADC got cancelled? I think that analog input (and streaming to HUB/LUT) would be very useful.
confused,
Mike
Comments
My older two kids and I passed through Clear Lake at 1am on Saturday morning, after a funeral we attended in Fort Bragg. I almost pm'd you to ask if we could sleep on your floor, since we were so tired from driving all day. We wound up making it all the way Williams before I pulled into a rest stop and fell asleep for two hours. We finally got home at 6am.
Good point. No use trying to test this in the FPGA.
The final DACs are to be solely bitstreamed? That makes sense but your use of flash DACs on the Prop123 had muddied my thinking.
The DACs are "flash", while the ADC is bitstreamed.
Good to know, that ADC is still in there. After the hills the way from Clearlake to Williams is quite boring. Good call to take a nap before entering HW5.
Don't hesitate next time, I always have space for some guests.
Enjoy!
Mike
the DACs settle quickly correct? It could be interesting to look at adding a high speed comparitor on P3, together with some Successive Approximation sequencing logic, could make for much faster ADCs
The DACs settle in under 3ns. I never thought about SAR, since we don't have a sample-and-hold circuit, but it could be done in software. The precision comparator takes about 30ns to react to 100mV, but much longer for 10mV. We'll see.
The other question chip is say I want to talk to a 2.5v or 1.8v system but the VIO is 3v3. Is there a mode where we can preset the DAC "high" voltage, then OUT just works like a usual digital output from software point of view? This could also be useful for a kind of emulated LVDS
You would just configure the low-level pin as a comparator input and it would return the comparator output on IN. The companion pin is always the odd/even neighbor.
We could make a digital mode like you describe, but the problem is that the DACs take static current. Running 8 of them would be maybe okay in 1k-ohm mode, but it would take a lot current in 75-ohm mode (8 * 13mA = 104mA). To go along with digital DAC output, there is an internal DAC in each pin which can drive the other side of the comparator. Whatever value DAC level high is could be shifted right by one bit and used to drive the DAC for internal comparison. That would give DAC-level digital input and output. That would be a simple and useful thing to make a mode of.
I had to think about this for most of the day, but found a nice way to implement it using what were the PINSETM %T and %D bits. They are combined to make %TT now, which is mode-dependent. I think we've got it all covered.
I also added A-edge to B-edge timer modes into those four blank slots. I just extended the measuring block to cover it. Very little logic was required.
If you go to the main documentation link (not the intermediate doc), I've added to the end a new smart pin description, in preparation for a new whole release.
PINSETM now uses #1, not #0 for D to signal PINACK. This means that pins can be reset with #0 now, instead of #1.
The smart pins are now done, barring any bug fixes.
Sounds good,
Is there Atomic control of such paired counters ?
ie can they reset / arm on the same SysCLK edge ?
I know you've explained this 10 times, but I'm not sure if they can in the way you mean. They can brought out of reset at the same time.
Sounds really good, Chip.
I have a request relating to the streamer, although perhaps there is already a way to do this. The streamer data can operate in NCO mode right up to full sysclock (80 MHz currently), but (I think) the maximum clock rate that can be generated is half sysclock, 40 MHz (accumulating $80000000 on each cycle for 1:1 toggling output)
If the above is correct, would it be possible to have a mode where, if the accumulation is > $80000000 and results in a MSB '1' , then it ORs with the system clock to generate a pulse (6.25ns high, then 6.25ns low) ? That'd let us work with high speed dacs like the video one you used on the a9, as well as perhaps getting above 148 MHz hdmi in the final silicon.
The existing CIO inversion at pin level could be used to change the phase if required.
That is tough to do because it violates synchronous timing rules. I know it's possible, but I really shied away from things like that with synthesis. Maybe this could be revisited before the chip is done.
If the mechanism is there to bring multiple counters out of reset on the same SysCLK edge, that sounds very close.
Can that same mechanism not be used for Capture Enable/Disable/Arm, across more than one counter ?
What you could do, as an interim solution, to allow some testing, would be to allow output the SysCLK to a pin ?
Many MCUs have that ability.
If that could also have a count number, that would be more flexible.
High MHz is always going to push the pin slew/slew abilities, but this may allow a lower overall SysCLK in designs too.