de0 1 .jic? vid?

rjo__ · 2013-09-27 15:54

Hello again.

I am using a bare de0-nano. After programming the Nano using Chip's latest .jic file to allow SDRAM access, I can't find
the P2. If I use the old .jic, the driver compiles and loads, but doesn't work(of course). I'm sure that this issue has already been raised and answered, but after several hours of looking I'm coming up empty.

I think this problem is from a remapping of the Nano's pins to connect to the adapter board? Where are p90,91?

Is the pin map for the other header changed? Is there a new map?

Question 2:

I would like to look at some of the video drivers... starting with NTSC.
If I use pin0 for the NTSC, do I add a single resistor or do I need a resistor to ground as well?

Thanks.

ozpropdev · 2013-09-27 16:21

Hi rjo__

I believe your correct. My recollection is the later DE0 binary is for the add-on boards.
As for the NTSC driver, it still uses the DAC so again a add-on board is required.
It looks like we need more add-on boards for the DE0 & DE2.

Cheers
Brian

Ariba · 2013-09-27 18:32

new PropPlug pins

Andy

David Betz · 2013-09-27 19:20

ozpropdev wrote: »

Hi rjo__

I believe your correct. My recollection is the later DE0 binary is for the add-on boards.
As for the NTSC driver, it still uses the DAC so again a add-on board is required.
It looks like we need more add-on boards for the DE0 & DE2.

Cheers
Brian

I think Parallax may still have a few of the add-on boards.

rjo__ · 2013-09-27 20:17

Thanks everybody.

Andy... so where is ground?

David... this forum and those precious few add-on boards are for really serious developers... I'm really not:) If you will notice, I have asked a lot of questions and have a lot of opinions, but I have contributed nothing!!! This trend is likely to continue into at least the near future.

The last thing I would want to do is ask for a freebee... have Ken exhaust his supply... and then the next genius comes along and there is nothing there for him.

I would be happy to buy one... if anyone is selling:) Ken isn't:(

I can live without one for the time being, but hopefully not for long.

Rich

Ariba · 2013-09-27 21:22

rjo__ wrote: »

Andy... so where is ground?
....

I let this as an exercise for you. A little hint: Ground pins are not configurable and stays therefore always at the same header pins ;-)

Andy

rjo__ · 2013-09-28 10:26

Andy... a riddle!!! I love riddles. Thanks for the hint.
Rich

potatohead · 2013-09-28 11:03

Rjo, I have a Nano add on board and will send it to you. PM me with your address details.

rjo__ · 2013-09-28 18:38

Mr. Potatohead

Your offer is too kind and greatly appreciated. PM is in the ether.

Andy

Thanks to you I have some good news: I am now communicating with my Nano-Prop, using the configuration file (.jic) that supports the SDRAM driver. The bad news is that the the SDRAM_Driver_DE0.obj file loads, but then hangs. Unless anyone has a suggestion, I will wait for the add-on board from Potatohead... and if it still doesn't work, assume I damaged my little Nano and get a new one.

I don't want to wait... so if there is something I need to figure out... fire away.

Thanks again

Rich

ozpropdev · 2013-09-28 19:34

Hi rjo__

Does your SDRAM driver use the "ORGH $18E80" directive instead of "ORGH $E80"?
Just an idea

Cheers
Brian

rjo__ · 2013-09-28 20:06

Cheers,

I am using the prior version of PNUT, which had the HUB memory constraint. The driver just uses org

' SDRAM Driver Demo for DE0-Nano
'
'	- executes Command List at hub $7000
'	- then returns to Monitor
'
' Enter Monitor commands with PropTerminal:
'
'	first compile the driver with PNUT (we need the .OBJ file later)
'	Reset Prop2
'	<SPACE>		'enter monitor
'	N		'switch to long mode to make the list:
'	7000:000F 0000	'List0: write hub 0000..03FF into SDRAM
'	7008:1007 0000	'List1: read SDRAM into hub 1000..13FF
'       7010:0008 0000	'List2: end of list
'       then upload the SDRAM_DRIVER_DE0.OBJ file with File-Upload menu
'	press <return> when you see 0+E80 to start the driver and execute the list once
'	<SPACE>		'enter monitor
'	1000.1111	'view 1000..1111 (or more)
'
DAT		org

		setptra sdram_par
		jmp	#sdram_driver

monitor_adr	long	$0070C
monitor_par	long	90<<9 + 91

sdram_par	long	$7000




'********************************
'*				*
'*  Propeller II SDRAM Driver	*
'*     for 16M x 16 devices	*
'*	  (FPGA version)	*
'*				*
'*  Version 0.1			*
'*  9 April 2013		*
'*  by Chip Gracey		*
'*				*
'********************************

{
SDRAM connections:

	P85 = cke (held high)		Port C
	P84 = cs
	P83 = ras
	P82 = cas
	P81 = we
	P80 = udqm (not used)
	P79 = ldqm (not used)
   P78..P77 = ba[1..0]
   P76..P64 = a[12..0]

   P63..P48 = dq[15..0]			Port B


  Note:	All pin directions have a 2-clock delay
	All pin outputs going to SDRAM have a 3-clock delay, since they are registered at the pin
	All pin inputs coming from SDRAM have a 2-clock delay, since they are registered at the pin


Commands (pairs of longs):

name		quads	bytes	hub_address (+0, set 2nd)			sdram_address (+1, set 1st)
------------------------------------------------------------------------------------------------------------------------
rw_1024		64	1024	%xxxx_xxxx_xxxx_xxxA_AAAA_AAAA_AAAA_W111	%xxxx_xxxA_AAAA_AAAA_AAAA_AA00_0000_0000
rw_512		32	 512	%xxxx_xxxx_xxxx_xxxA_AAAA_AAAA_AAAA_W110	%xxxx_xxxA_AAAA_AAAA_AAAA_AAA0_0000_0000
rw_256		16	 256	%xxxx_xxxx_xxxx_xxxA_AAAA_AAAA_AAAA_W101	%xxxx_xxxA_AAAA_AAAA_AAAA_AAAA_0000_0000
rw_128		 8	 128	%xxxx_xxxx_xxxx_xxxA_AAAA_AAAA_AAAA_W100	%xxxx_xxxA_AAAA_AAAA_AAAA_AAAA_A000_0000
rw_64		 4	  64	%xxxx_xxxx_xxxx_xxxA_AAAA_AAAA_AAAA_W011	%xxxx_xxxA_AAAA_AAAA_AAAA_AAAA_AA00_0000
rw_32		 2	  32	%xxxx_xxxx_xxxx_xxxA_AAAA_AAAA_AAAA_W010	%xxxx_xxxA_AAAA_AAAA_AAAA_AAAA_AAA0_0000
rw_16		 1	  16	%xxxx_xxxx_xxxx_xxxA_AAAA_AAAA_AAAA_W001	%xxxx_xxxA_AAAA_AAAA_AAAA_AAAA_AAAA_0000
skip_done	 0	   0	%0000_0000_0000_0000_0000_0000_0000_0000	%xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
end_of_list	 0	   0	%0000_0000_0000_0000_0000_0000_0000_1000	%xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx


The driver scans a list for commands. Commands take two longs and are structured as hub_address + sdram_address. To have
the driver perform a read or write operation on the SDRAM, first set the sdram_address (2nd long) and then the hub_address
(1st long). The driver will set each hub_address long to skip_done (0) when its associated operation has completed.

Before starting the driver, build the command list structure with pairs of 0's, then terminate it with an 8. When launching
the driver into a cog, point the parameter (S) to the start of the command list.


Command list (longs):

	hub_address (skip_done/rw_xxxx)
	sdram_address

	hub_address (skip_done/rw_xxxx)
	sdram_address

	hub_address (skip_done/rw_xxxx)
	sdram_address

	...

	end_of_list
}

'
'
' Initialize SDRAM				clocks	hub	
'						----------------
sdram_driver	getptra	list			'1	-		save command list address

		reps	#6000,#1		'1	-		repeat instruction for 100us @60MHz
		mov	pinc,h003FFFFF		'1	-		cke and cs high
		mov	dirc,h003FFFFF	wz	'6000	-		set SDRAM signals to outputs (100us), Z = 0
'
'
' Scan list for commands
'
:finish	if_z	wrlong	cmd,ptra[-2]		'1	0		if command finished, set it to skip_done (cmd = 0)

		mov	pinc,h00240400		'1	1		issue 'precharge all' command
		setb	pinc,#20	wz	'1	2		deselect, Z = 0
:reset	if_z	setptra	list			'1	3		if end_of_list, reset list pointer; satisy Trp

		mov	pinc,h00200037		'1	4		issue 'set mode' command
		setb	pinc,#20		'1	5		deselect, satisfy Tmrd

		mov	pinc,h00226000		'1	6		issue 'auto refresh' command
		setb	pinc,#20		'1	7		deselect, satisfy Trfc in 8 more clocks

:next		rdlong	cmd,ptra++[2]	wz	'3	0..2		check command, point to next
		setptrb	cmd			'1	3		in case command, set hub address
	if_z	jmp	#:next			'1/4	4/4..7		if skip_done, next command

		decod3	cmd		wc	'1	5		decode size bits, C = write
		and	cmd,#%11111110	wz	'1	6		isolate bits 7..1, Z = 1 if end_of_list
'	if_z	jmp	#:reset			'1/4	7/7..2		if end_of_list, reset list pointer
	if_z	jmp	#monitor		'1/4	7/7..2		if end_of_list, return to monitor
'
'
' Execute read/write command			clocks	hub	XFR write SDRAM		XFR read SDRAM
'						------------------------------------------------------
		rdlong	adr,ptra[-1]		'3	0..2	-			-			get SDRAM address

		shl	adr,#7			'1	3	-			-			make 'active' command with bank and row address
		or	adr,#%1_0011_00		'1	4	-			-			(ba[1..0], a[12..0]) = adr[24..10]
		rol	adr,#15			'1	5	-			-

		mov	pinc,adr		'1	6	-			-			issue 'active' command
		setb	pinc,#20		'1	7	-			-			deselect, satisfy Trcd in 1 more clock

	if_c	rdquad	ptrb++			'1	0	-			-			if write, read initial QUADs from hub

		setbc	:quad,#0		'1	1	-			-			set wrquad/rdquad according to read/write

	if_c	setxfr	#%010_011		'1	2	<QUADs_to_16_pins>	-			if write, configure XFR at hub cycle 2

		shr	adr,#22+1		'1	3	-			-			make blank command with bank and column address
		and	pinc,h00306000		'1	4	-			-			(ba[1..0], a[12..0]) = (adr[24..23], %0000, adr[9..1])
		or	pinc,adr		'1	5	-			-

	if_c	mov	dirb,hFFFF0000		'1	6	-			-			if write, enable data outputs

	if_nc	setxfr	#%100_011		'1	7				<16_pins_to_QUADs>	if read, configure XFR at hub cycle 7

	if_nc	xor	pinc,h001A0000		'1	0	-			-			if read, issue 'read' command
	if_nc	setb	pinc,#20		'1	1	-			-			if read, deselect

	if_c	xor	pinc,h00180000		'1	2	-			-			if write, issue 'write' command (aligns with XFR on next clock)
	if_c	setb	pinc,#20		'1	3	output QUAD0 w0		-			if write, deselect; read: SDRAM sees 'read' command

		shr	cmd,#1			'1	4	output QUAD0 w1		-			get loop count

	if_nc	nop	#7			'1	5	output QUAD1 w0		-			if read, pad time
		'(nop)				'1	6				-			read: SDRAM starts outputting data stream
		'(nop)				'1	7				-
		'(nop)				'1	0				input w0		read: SDRAM data stream begins arriving in XFR
		'(nop)				'1	1				input w1 -> QUAD0
		'(nop)				'1	2				input w0
		'(nop)				'1	3				input w1 -> QUAD1
		'(nop)				'1	4				input w0

:quad		'(wrquad/rdquad)		'1	5	output QUAD1 w0		input w1 -> QUAD2
		'(wrquad/rdquad)		'1	6	output QUAD1 w1		input w0
		'(wrquad/rdquad)		'1	7	output QUAD2 w0		input w1 -> QUAD3
		wrquad	ptrb++			'1	0	output QUAD2 w1		input w0		write: read next QUADS; read: write current QUADS
		djnz	cmd,#:quad		'1	1	output QUAD3 w0		input w1 -> QUAD0	loop for each set of QUADs
		'(djnz looping)			'1	2	output QUAD3 w1		input w0
		'(djnz looping)			'1	3	output QUAD0 w0 (new)	input w1 -> QUAD1	write: RDQUAD data valid
		'(djnz looping)			'1	4	output QUAD0 w1		input w0

		mov	pinc,h002C0000		'1	2	output QUAD3 w1		-			issue 'burst terminate' command (aligns with XFR on next clock)
		mov	dirb,#0		wz	'1	3	-			-			cancel data outputs (aligns with 'burst terminate'), Z=1
		jmp	#:finish		'4	4..7	-			-			finish up, scan for next command

monitor		setcog	#0				'return to monitor
		coginit	monitor_adr,monitor_par

'
' Constants
'
h00180000	long	$00180000		'write' command toggle
h001A0000	long	$001A0000		'read' command toggle
h00200037	long	$00200037		'set mode' command (full-page r/w bursts, cas latency = 3)
h00226000	long	$00226000		'read' command mask
h00240400	long	$00240400		'precharge all' command
h002C0000	long	$002C0000		'burst terminate' command
h00306000	long	$00306000		'blank command mask
h003FFFFF	long	$003FFFFF		'control pins mask
hFFFF0000	long	$FFFF0000		'data pins mask
'
'
' Variables
'
list		res	1			'command list pointer
cmd		res	1			'command
adr		res	1			'address

Ariba · 2013-09-28 23:51

rjo__

Yes it hangs, if you do it exactly according that description.
You need to switch back to byte mode before you upload the .obj file (just type Y before you open the menu). I have that added to the description later, but not posted as an update.
This driver was just a short test after Chip released his SDRAM driver, you can not do something useful with it in one cog.

Attached is another driver I made, that provides subroutines to init the SDRAM, and for read and write a quad. A quad is the minimal granulation (granularity?) you can read and write with this code.
I hope the description at begin is clear enough. You don't need the monitor to write and check the SDRAM, the serial routines and hex handling are all bulit in.

Andy

rjo__ · 2013-09-29 18:58

Andy,

Thanks again.

My nano-P2 is alive and storing data. One issue I ran into with the above file was that the high word of q3 was read inaccurately. For small values, if the intended (low word) value was x, the high word of q3 was generally x-(x mod 2).

I tracked this down to a nop after the ramRead_ret retd

ramRead shl	adr,#7			'Read one Quad from SDRAM (16 bytes)
	or	adr,#%1_0011_00		'make 'active' command with bank and row address
	rol	adr,#15			'(ba[1..0], a[12..0]) = adr[24..10]
	mov	pinc,adr		'issue 'active' command
	setb	pinc,#20		'deselect
	shr	adr,#22+1		'make blank command with bank and column address
	and	pinc,h00306000		'(ba[1..0], a[12..0]) = (adr[24..23], %0000, adr[9..1])
	or	pinc,adr
	xor	pinc,h001A0400		'issue 'read' command with AutoPrecharge
	setb	pinc,#20		'deselect
	nop	#3			'wait until SDRAM outputs data (3+2 clocks PinDel+CASlatency)
	setxfr	#%100_011		'<16_pins_to_QUADs>
	nop	#4			'read QUAD0 w0 .. QUAD2 w0
ramRead_ret	retd			'read QUAD2 w1
'	nop	#1			'read QUAD3 w0 .. QUAD3 w1  <---- this was changed to a comment
	setxfr	#0			'stop Quad input transfer

Correct me if I a mistaken on this:
nop #4 ... should take 16 clocks (4*(n=4)), required by the setxfr mode. So, I assume the extra 4 clocks created by NOP #1 shifted the value in q3 over by 4 bits, but why does this timing issue have anything to do with a single bit error in the high word of q3?

Ariba · 2013-09-30 08:33

You are right, the high word of the 4th long is not correct.

But the error is not in the Read, but in the Write routine. It seems the XFR transfer is stopped one cycle to early and w0 and w1 have always the same value.
I set up the SDRAM in a burst-8 mode, so the RAM stops every Read or Write command after 8 clocks, also if the Prop outputs or reads more data. So it could be only the Write with 1 XFR cycle too short.

Attached is the corrected version. The Read routine takes now also 1 cycle less.

Andy

Edit: NOP #4 takes 5 clocks, that is one nop + the #number additional nops. On Prop2 single cycle instructions take only 1 clock.

rjo__ · 2013-10-03 07:20

Hi Andy,

Yesterday, I got my first chance to set down with sdram_test1_1.spin and behold, Chip sent a major update our way:)

My still bare nano-P2 is running fine. I am using your Prop2 terminal 0.5?

I made the obvious changes to the sdram_test1_1.spin, changed clock speed to 80_000_000, changed the 200usec delay code to repeat 16000,
and set the monitor re-entry to $700.

The terminal locks up. I can reset the Prop and get the monitor.

I have looked through the code three times... have no clue(:

By the way, I love your terminal... do you have documentation? Google doesn't find Prop2 terminal, I can't remember where I found it, and I don't see anything yet on your website.

Thank you very much

Rich

Ariba · 2013-10-03 14:31

rjo_

You can set the clkfrq to 20 MHz, or use the attached version which does a clkset to 80 MHz.

There is some PropTerminal description in the Sticky thread here.
Prop2Terminal is just a little variation of the PropTerminal, the difference is that it allows to upload an object file over the P2-Monitor. You can use the description for PropTerminal in the ZIP files (I know that textfile is a mess).

Andy

rjo__ · 2013-10-04 05:58

Andy,

Thanks for the info and effort.

Still no love from my Nano.
I am running a bare NanoP2. A couple of posts seem to indicate that this might be the problem. Chip has indicated that he believes there is a timing issue, which he plans to address. I can't get your cordic code to run either. I can get a "hello prop2" example to run, which uses your terminal.
I should be getting an add-on board from Mr. Potatohead soon. So, hopefully that will get me up and running.

Have you run this on a bare Nano?

Thanks again.

Rich

de0 1 .jic? vid?

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