[resolved][puzzle] missing piece, The

kuroneko · 2012-10-26 00:33

Below is some code doing C3's SPI selection using a clkfreq/2 counter. arg0 is the required ID (0..7).

DAT

spi_set         add     :jmp, arg0              ' prime call
                movi    outa, #0                ' reset decoder
                movi    outa, #|< (SPI_SEL_CLR - 23)
:jmp            jmpret  $, $+1 wc               ' call sub function
                
spi_set_ret     long    0-0, s1, s2, s3, s45, s45|NEGX, s67, s67|NEGX

s1              movi    phsb, #%00000000_0      ' 1 pulse
                movi    phsb, #%10000000_0
                jmp     spi_set_ret

s2              movi    frqb, #%10000000_0      ' 2 pulses
                movi    frqb, #%00000000_0
                jmp     spi_set_ret

s3              movi    frqb, #%10000000_0      ' 3 pulses
                [COLOR="red"]???[/COLOR]
                jmp     spi_set_ret
                
s67             movi    frqb, #%10000000_0      ' 6/7 pulses
s45             movi    frqb, #%10000000_0      ' 4/5 pulses
        if_c    waitpne $, #0
                movi    frqb, #%00000000_0
                jmp     spi_set_ret

CON
  SPI_SEL_CLK = 8
  SPI_SEL_CLR = 25

The counter setup is as follows:

DAT
                movs    ctrb, #SPI_SEL_CLK      ' clock pin
                movi    ctrb, #%0_00100_000     ' NCO
                movi    phsb, #%10000000_0      ' preset (high)

Question: What is the missing instruction?

Phil Pilgrim (PhiPi) · 2012-10-26 10:25

Without over analyzing your code, I'll make a wild guess:

                jmp     #s2 + 1

But then, you wouldn't need the following jmp, would you.

-Phil

Edit: Oh, wait; that gives four pulses. Hmmm.

Mark_T · 2012-10-26 14:56

Yes, its the even number of pulses thing that's requiring deviousness... I'm guessing something that can take 6 cycles, perhaps:

                waitpne frqb, #0  wr

The test will succeed since 0 anded with INA will never equal FRQB, and forcing the result to be written will plonk that 0 in FRQB, hopefully 6 cycles
after the previous instruction wrote FRQB.

kuroneko · 2012-10-26 16:13

Mark_T wrote: »

The test will succeed since 0 anded with INA will never equal FRQB, and forcing the result to be written will plonk that 0 in FRQB, hopefully 6 cycles after the previous instruction wrote FRQB.

It's getting warm (timing is correct now), the only problem/issue is that all wait??? instructions use add as their primary instruction. So in this case frqb won't be 0 to disable the counter.

Phil Pilgrim (PhiPi) · 2012-10-26 16:23

Well, then

          waitpne  frqb,frqb wr

$8000_0000 + $8000_0000 == 0.

-Phil

kuroneko · 2012-10-26 16:29

One, how do you make sure that it's not equal (i.e. ina[31] == 1). While this can be arranged it's not reliable (usually serial RX). Second, waitpne is special for some reason, result := dst + src + 1 (which makes it so much easier to avoid point one).

Phil Pilgrim (PhiPi) · 2012-10-26 16:33

This is like pulling teeth.

Okay, that's pretty clear then:

          waitpne    frqb, _0x7fff_ffff wr

-Phil

kuroneko · 2012-10-26 16:40

One of the short ones it seems (puzzle that is). Thanks for participating.

Phil Pilgrim (PhiPi) · 2012-10-26 16:47

Any idea what the logic might have been behind the +1? And why the sum to begin with I wonder.

-Phil

kuroneko · 2012-10-26 16:58

[black box observation mode] I blame waitcnt (all wait??? are part of the same 4n group), i.e. use what's there and just change the trigger h/w. As for the +1, your guess is as good as mine but it seems to coincide with eq/ne which is good enough for me (to keep them apart that is). A bit like addx behaviour ...

Mark_T · 2012-10-26 17:29

Ah, that would have been so much harder without telling us the +1 thing! Truly devious.

User Name · 2012-10-26 20:49

Why only 176 views (at this moment in time)?? As I scan the list of threads each day, Kuroneko's puzzles and Prop2 updates are the only two topics that always earn a click.

[resolved][puzzle] missing piece, The

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