analyzing clock jitter
darreno
Posts: 16
Anyone know of way to determine how much cycle to cycle jitter a clock has without having a spectrum analyzer?
The clock under test is up to 4MHz. I'm thinknig a propeller counter could only be used to find really large instabilities. Will a 20ppm crystal keep a propeller's clock accuracy near 20 ppm?
The clock under test is up to 4MHz. I'm thinknig a propeller counter could only be used to find really large instabilities. Will a 20ppm crystal keep a propeller's clock accuracy near 20 ppm?
Comments
This is all theory, which I may be not fully understanding.
A question about the WAITPEQ, does it start the next instruction on the next clock cycle or after 6 cycles. I don't understand if the 6 cycle time for the instruction includes any latency after the condition is met.
I'm assuming you meant to mix 1MHz with 980KHz ???
One way is as you describe. Mix (xor) the two frequencies the result will be the sum and the difference. Then filter off the sum (low pass filter). That is how we did it in this video http://www.youtube.com/watch?v=fkYL7fluv5E
If I was doing it again, I would try sampling the 980KHz at 1MHz (1 million samples per second). This should be possible with PASM. The sampled pin should change state at 20KHz. You would count how many samples are high, then how many samples are low. The change in high or low counts will be the jitter.
If you want to try this method I could help you with the code. Let me know in this thread.
Bean
-Phil
IIRC WAITPEQ takes 6 cycles to 'get going' but thereafter it will sync to 1 clock, not the usual 4.
What time frame jitter do you want ? Do you mean measure the ppm error, or do you expect more jitter on this.4MHz ?
Generating Fsys/2^N will avoid any NCO rounding jitter, but it will have PLL jitter.
You could mix this down to an Audio range, and then use a Sound Card to get the spectrum which will give more info about the jitter.
This all came about when I started playing with a Si5351 clock generator. It's a fractional N clock that is very cheap but advertises a high max jitter (100ps). The datasheet doesn't say much about how to calculate the jitter given a choice of divisors so I though I'd learn how to measure it myself. I found out that jitter analysis tools even for a moderate clock rate can be expensive.
I think I may try a few different methods so I can compare them.
-Phil
This may be an entire waste of time other than a good learning experience.
'Different app, but similar issues and a solution like what you're proposing.
-Phil
Look at the report file for the Si5351, and you can 'work backwards'
It has a choice of pre-PLL lock, and post PLL - the Post PLL works like a NCO, so does a fractional divide from the VCO, and that will jitter at the VCO frequency.
They do mention the VCO somewhere, IIRC just under 2GHz, so peak jitter can be derived from that.
If you avoid the post-fractional, then the jitter will be much less.
If you want to test this more, the best way is likely to use TWO Si5351, and get the reports and then use the beat system then to check jitter.
jmg, I'm not sure I understand what you mean by the report files for the 5351. Here's what the summary output of the "clock builder" application.
PLL A
Input Frequency (MHz) = 25.000000000
VCO Frequency (MHz) = 800.000000000
Feedback Divider = 32
SSC disabled
PLL B
Input Frequency (MHz) = 25.000000000
VCO Frequency (MHz) = 656.640000000
Feedback Divider = 26 166/625
Output Clocks
Channel 0
Output Frequency (MHz) = 0.100000000
Multisynth Divider = 250
R Divider = 32
PLL source = PLLA
Initial phase offset (ns) = 0.000
Inverted = No
Drive Strength (mA) = 8
Disable State = Low
Channel 1
Output Frequency (MHz) = 0.090000000
Multisynth Divider = 228
R Divider = 32
PLL source = PLLB
Initial phase offset (ns) = 0.000
Inverted = No
Drive Strength (mA) = 8
Disable State = Low
http://forums.parallax.com/showthread.php?135563-Measure-the-speed-of-electricity...
In one of the posts Bean said "The reading are pretty jittery".
I'm wondering now if that was just the result I'm looking for.
Here are the relevent lines, with the rest deleted
PLL A
Input Frequency (MHz) = 25.000000000
VCO Frequency (MHz) = 800.000000000
Feedback Divider = 32
PLL B
Input Frequency (MHz) = 25.000000000
VCO Frequency (MHz) = 656.640000000
Feedback Divider = 26 166/625
Output Clocks
Channel 0
Output Frequency (MHz) = 0.100000000
Multisynth Divider = 250
R Divider = 32
Multisynth Divider = 228
R Divider = 32
Note Silabs also have an option to have fractional post PLL dividers, which I think SiLabs call Multisynth Divider & R Divider
- so the channel with no fractional numbers at all, would make a good beat choice for a channel chosen to have fractional
Feedback Divider, or fractional Multisynth Divider
- so you can then measure the effect of the 'closer average value' has on the peak jitter.
Even a LV4046 would be useful here, as the sub 1ns phase change will show up on the Phase Detector output, as a level change, at rates shown by the Egyptian fractions - and a Narrow Pulse PhaseDet will have more mV/ns gain, than the XOR PhaseDet.