New ROM with updated SD booter and TAQOZ.
Extra register on each IN signal from pins to ensure metastability.
Fixes r/w glitch during LUT sharing.
Fixes JMP-event-within-REP bug.
'GETCT reg WC' doesn't change C.
This is for anyone who wants to try the next version of silicon, including the new ROM:
cogs smart pins RAM Freq CORDIC Filename
Prop123-A9 | 8 0-39,56-63 512k * 80MHz Yes Prop123_A9_Prop2_v33k.rbf
BeMicro-A9 | 8 0-39,56-63 512k * 80MHz Yes BeMicro_A9_Prop2_v33k.jic **
Prop123-A7 | 4 0-15,62-63 512k 80MHz Yes Prop123_A7_Prop2_v33k.rbf
DE2-115 | 4 0-7,60-63 256k 80MHz Yes DE2_115_Prop2_v33k.pof
* Allows loading up to $FFFFF to rewrite ROM.
** I had a file overwrite and I don't think that the SD card pins are mapped properly
anymore to P[61:58] on the BeMicro-A9 image.
Here are the differences between the current silicon and these next-silicon FPGA images:
RDLUT and WRLUT now support PTRA/PTRB expressions. This means immediate LUT addresses are limited to $000..$0FF, unless ## is used.
PTRA/PTRB expressions are now encoded slightly differently to allow wider address ranging. These are used by
RDBYTE/RDWORD/RDLONG/WRBYTE/WRWORD/WRLONG/WMLONG, and now also RDLUT/WRLUT. The version of PNut.exe included in the .zip file handles all this. You don't need to do anything. PNut.exe will assemble proper object code from your PASM source code.
The system counter (CT) has been extended to 64 bits. 'GETCT reg WC' returns the top 32 bits of the 64-bit system counter, clears C, and shields the next instruction from interrupts, so that a time-aligned reading of both halves can be made by following 'GETCT high WC' with 'GETCT low'.
There are two new instructions which set up and read the scope mode: 'SETSCP D/#' and 'GETSCP D'. SETSCP points the scope mux to a set of four pins starting at (D[5:0] AND $3C), with D=1 to enable scope operation. Any time GETSCP is executed, the lower bytes of those four pins' RDPIN values are returned in D. This feature will mainly be useful on the next silicon, as the FPGAs don't have ADC-capable pins.
Lastly, the USB smart pin modes have changed. There used to be four different USB modes ranging in %110xx. USB mode is now %11011 with WXPIN bits 15 and 14 setting the sub-modes and bits 13..0 setting the NCO frequency, as before, since bits 15 and 14 were always '0', anyway. Now, bit 15 = 0 for device mode or 1 for host mode, and bit 14 = 0 for low-speed mode or 1 for full-speed mode.
Smart pin modes %1100x are SINC2/SINC3/raw ADC modes, while smart pin mode %11010 is Scope mode. These aren't very useful until the next silicon exists, so there's no need to elaborate, yet.
I think those are the only changes.
Wait, better review this list of changes, too, since now all instructions that affect bits can now affect a RANGE of bits. You'll need to make sure you're not inadvertently affecting more than one bit, unless you intend to:
The .spin2 files in the .zip have all been modified to take advantage, where possible, of the new bit/pin-range operations.