New P2 Silicon

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Comments

  • Chip,
    Just testing details of the %FFF logic input block and bumped into what seems to be a flaw with the streamer. I went to serially send out a bitstream using immediate S register data. So 32 bits all up. And decided it would be easier to follow my own progress if I could shift out most significant first. So I set bit 16 (the "a" bit) in the streamer mode. The result is certainly not in bit significance order!

    Everything looks fine in least significant order when mode bit 16 is unset.

  • evanh wrote: »
    Chip,
    Just testing details of the %FFF logic input block and bumped into what seems to be a flaw with the streamer. I went to serially send out a bitstream using immediate S register data. So 32 bits all up. And decided it would be easier to follow my own progress if I could shift out most significant first. So I set bit 16 (the "a" bit) in the streamer mode. The result is certainly not in bit significance order!

    Everything looks fine in least significant order when mode bit 16 is unset.

    The "a" bit just reorders bits/twits/nibs within the individual bytes. I see I need to explain this in the doc. Will do so now.
  • evanhevanh Posts: 9,442
    edited 2020-04-17 - 07:29:59
    So with the "a" bit set, the immediate #S value is treated as four bytes - least byte first with each byte having most bit first - rather than one longword with most bit first. Right?

    PS: Mode number is %0100 "imm 32 x 1".

  • evanh wrote: »
    So with the "a" bit set, the immediate #S value is treated as four bytes - least byte first with each byte having most bit first - rather than one longword with most bit first. Right?

    PS: Mode number is %0100 "imm 32 x 1".

    That's right.
  • evanhevanh Posts: 9,442
    edited 2020-05-06 - 06:21:07
    Chip,
    After the boot options, in the main doc, there is a description of the boot sequences. It's missing the part about SD card booting.

    EDIT: That's something the community could submit now I think about it. :)

  • Thanks, Cluso.
  • I finally got the 'DEBUG INTERRUPT' section done in the Google Doc linked to in the first post of this thread.

    What was there before was outdated and incomplete. Now that I have this documentation complete, though lacking examples, I have enough reference material to make an initial debugger that I will hook into PNut and later the PropTool.
  • is the verilog code of the P2 open source?
    can we have a peek in your genius mind?
  • Surac wrote: »
    is the verilog code of the P2 open source?
    can we have a peek in your genius mind?

    He has not made it open source, though he has shared an occasional snippet during development. He has stated in the past that he eventually plans to open source it (if I'm recalling correctly), but not until a later time.
  • cgraceycgracey Posts: 12,793
    edited 2020-05-24 - 17:54:43
    Surac wrote: »
    is the verilog code of the P2 open source?
    can we have a peek in your genius mind?

    It's not open-source, but maybe it will be someday. It is more than 10 times as complex as P1, in terms of logic, and would take a commitment to get a handle on. If there's anything that is mysterious about any of it, I can provide more detail. I've written the documentation to cover all functional aspects, so people should have all the information necessary to program it for whatever it can possibly do.

    I found a picture that illustrates the mental workshop where it all happens.


    BOY-MY-GARGE-NEEDS-A-OVERHAUL-PLUS-.jpg
  • cgracey wrote: »
    I found a picture that illustrates the mental workshop where it all happens.


    BOY-MY-GARGE-NEEDS-A-OVERHAUL-PLUS-.jpg

    Chaos is just a higher form of order.
  • What can I say :smiley:
  • That workbench looks usable! I reckon there'll be floor space to stand at the bench too.

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