ADC Sampling Breakthrough

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  • TonyB_TonyB_ Posts: 1,226
    edited 2019-01-28 - 22:30:07
    cgracey wrote: »
    After some experimentation, I found that periodically clearing the first integrators in the Goertzel circuit, by temporarily switching from Sinc2 to Sinc1, and back to Sinc2, gets rid of the buildup problem.

    Does changing the mode always reset the integrators, so switch to Sinc1 can be followed immediately by switch back to Sinc2?
    Formerly known as TonyB
  • TonyB_ wrote: »
    cgracey wrote: »
    After some experimentation, I found that periodically clearing the first integrators in the Goertzel circuit, by temporarily switching from Sinc2 to Sinc1, and back to Sinc2, gets rid of the buildup problem.

    Does changing the mode always reset the integrators, so switch to Sinc1 can be followed immediately by switch back to Sinc2?

    Correct. During Sinc1 mode, the first integrators always hold the scaled sin and cosine, without accumulating them, like in Sinc2 mode.

    On each clock, the first integrators are added into the second integrators, which get cleared on GETXACC.
  • Bob Lawrence (VE1RLL)Bob Lawrence (VE1RLL) Posts: 1,546
    edited 2019-01-29 - 01:17:20
    @ cgracey
    After some experimentation, I found that periodically clearing the first integrators in the Goertzel circuit, by temporarily switching from Sinc2 to Sinc1, and back to Sinc2, gets rid of the buildup problem.

    The new Goertzel circuit allows up to 4 ADC input pins with selectable polarity for each. This is going to make relative measurements possible, among other things.

    In these videos, there is a stable 1MHz sine coming into one pin and a swept sine above and below 1MHz coming into another pin. The two pins are summed to form the input sample. The sample is then multiplied each clock by cosine and sine values which are accumulated and periodically converted to power (hypotenuse).

    For the Sinc2 video, I'm clearing the first integrators at the outset of each swept-sine measurement. You can see the resolving difference between Sinc1 and Sinc2 quite nicely.

    Thanks! for the video's Chip, that's very cool.
  • This is going to make relative measurements possible, among other things.

    I wonder what chip means by other things and What kind of other measurements may be possible ? :)


  • I've thought for a long time that the Goertzel hardware could be used for windowed ADC sampling. But it would be tricky if we wanted to reduce the sample rate by anything other than a power of 2. It could be done if we calculate exactly what steps the Goertzel hardware would use and we put our coefficeints at those locations in the look up table. But what if we don't want to decimate the ADC data by an integer?


    For example, if we want exactly 640 samples per line of NTSC video, we need a sampling rate of 10.06976MHz. Note that I'm ignoring the blanking interval.

    We could divide the 250MHz sysclock by 24.827 to meet our desires. The problem with doing that is we will have some intervals with 25 sysclocks between samples and some intervals with 24 sysclocks between cycles. This will affect our ADC accumulators because integrating for a longer time will result in a larger output value. Maybe we could compensate for that. One of the main lessons in this thread is that we need a window filter to get good performance from the P2 ADC. For demonstration, I'll use a triangular window. There may be other choices that perform better.

    goertzel-sample-points.png
    Early Sampling 
    sample number     1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25
    sample position   7  17  27  38  48  58  69  79  89  99 110 120 130 141 151 161 172 182 192 203 213 223 234 244 254
    window value      6  16  26  37  47  57  68  78  88  98 109 119 126 115 105  95  84  74  64  53  43  33  22  12   2
    
    Late Sampling
    sample number      1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24
    sample position   10  20  30  41  51  61  72  82  92 103 113 123 134 144 154 164 175 185 195 206 216 226 237 247
    window value       9  19  29  40  50  60  71  81  91 102 112 122 122 112 102  92  81  71  61  50  40  30  19   9
    
                      Sum   N samples
    Early Sampling    1577     25
    Late  Sampling    1575     24
    

    Despite having a different number of samples in the interval, the full scale gain doesn't change that much. The gain variance as the number of samples changes is reduced from 4.1% to .13%. Maybe we could compensate for the deviation in the number of samples per interval. But we still need a window function to get good performance from the ADC. The beauty is that a carefully chosen window function will compensate for fractional resampling automatically. All we need to do is program our desired sample rate into the streamer's frequency register.

    This is just a one point test, it's not always this good. The gain varies with the stating phase and the sampling frequency. Over all starting phases, the peak-to-peak gain deviation is .32%

    The P2 ADC video quality looks quite good. The test images are from a TV connected to the propeller's DAC. One is composite direct to the TV for reference. Note that 10.x MHz is a little bit low for the highest quality video. If Chip has added modes to use multiple pins in parallel, that should produce very good video when using 2 or 4 ADC pins.

    1920 x 1440 - 602K
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    James https://github.com/SaucySoliton/

    Invention is the Science of Laziness
  • Saucy, we could use multiple pins in parallel with a common signal, summing their conversions. That could work with the scope mode, too. The biggest problem is that we have something like -3dB @1.5MHz on the ADC's analog front end.
  • potatoheadpotatohead Posts: 9,771
    edited 2019-08-24 - 20:52:07
    The standard sample is 13.500Mhz, and it's valid for NTSC and PAL. Most gear is running at that rate these days.

    Saucy, those captures are impressive!

    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
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  • Saucy, you could do this now on the V1 silicon: Run the NTSC baseband signal into four pins and sum their conversions, instead of just using one pin. You should get two more bits of quality that way.
  • The Goertzel function is new to me. I've got some learning to do.
    Prop2 Docs wrote:
    This mode uses the lookup RAM as a source of sine/cosine samples, such that bytes 3 and 2 must be unbiased signed sine and cosine values, and bytes 1 and 0 are biased (positive) sine and cosine values suitable for driving DACs. By incorporating DDS output with Goertzel input, many interactive real-world measurements can be made to determine things like time-of-flight and resonance.

    Question: I don't understand any general meaning of biased/unbiased. I suspect its meaning is situation dependant. You've labelled positive beside biased, is that what biased means there?

    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • evanh wrote: »
    The Goertzel function is new to me. I've got some learning to do.
    Prop2 Docs wrote:
    This mode uses the lookup RAM as a source of sine/cosine samples, such that bytes 3 and 2 must be unbiased signed sine and cosine values, and bytes 1 and 0 are biased (positive) sine and cosine values suitable for driving DACs. By incorporating DDS output with Goertzel input, many interactive real-world measurements can be made to determine things like time-of-flight and resonance.

    Question: I don't understand any general meaning of biased/unbiased. I suspect its meaning is situation dependant. You've labelled positive beside biased, is that what biased means there?

    By "biased", I meant that the MSB is inverted, so that it ranges from $01..$FF, whereas unbiased would range from -$7F..+$7F.

    In the new silicon, all Goertzel LUT bytes need to be unbiased. When output to the DACs, the Goertzel hardware will flip the MSB of each byte, making it suitable for DAC output.
  • Ah, right, of course. Here I was thinking it was more complicated even when you've stated it's to match the DACs.
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • SaucySolitonSaucySoliton Posts: 233
    edited 2019-09-06 - 05:43:11
    cgracey wrote: »
    Saucy, you could do this now on the V1 silicon: Run the NTSC baseband signal into four pins and sum their conversions, instead of just using one pin. You should get two more bits of quality that way.

    Combining multiple ADC pins is going to be the last thing I do. Since I use the Goertzel hardware for the window filter, it's one ADC per cog. I'd need to keep all of the cogs exactly in sync, while I vary the sampling frequency to lock onto the video source. What I will try is switching the ADC to 3.16x mode. That may need attenuation and AC coupling. It should improve the quality by using as much of the full ADC range as practical. Maybe we could add a pre-emphasis circuit to equalize the rolloff of the ADC a bit.

    The most important part of video input is synchronization. I'm working on that now. Then perhaps color decoding, because we all like that! We can sample at 13.5MHz, but should we? If we use 12.273MHz we get square pixels for NTSC. I think having a monochrome decoder in one cog is a good goal.


    The code I posted could be adapted to a scope filter with a max sampling rate of perhaps 20MS.
    James https://github.com/SaucySoliton/

    Invention is the Science of Laziness
  • I have an Idea about how to best utilize parallel ADCs. The last ~10 pages of this thread are about how the P2 ADC can't have an absolute accuracy better than 1/N where N is the number of clock cycles is the measurement interval. With windowing filters, we can get way more than N output levels. The problem is, at certain points in the ADC output range, like 1/3, the bitstream becomes too uniform to detect small changes in a short sampling time. That causes a non-linearity in the output at those points. It is thought that a second order or higher modulator would not be subject to this problem.

    If using 2 or more ADCs in parallel, it might be best to offset their ranges slightly. That way they both don't hit the non-linear points at the same time. The hardware would look like this:
    in-------o--|C]-----ADC 1
             |
            [R] 
             | 
             o--|C]-----ADC 2
             |
            [R]
             | 
    gnd------o----------GND
    
    AC coupling capacitors optional. For a video input, I would use them because 1. It's industry standard practice. 2. To run the ADCs in 3.16x mode, which results in a full-scale range of 1.56Vpp.
    James https://github.com/SaucySoliton/

    Invention is the Science of Laziness
  • Nice idea. There is quite a difference between the adc ranges from one channel to another, as well as from one chip to another. Thats why its necessary to do the autocalibration using GIO and VIO. So, the offset may not be so important, if the two channels are naturally sufficiently different

    The 3.16x makes a lot of sense too
  • Yes, that's a good idea, Saucy.

    In the future I would like to expand the ADC converters so that they work independent of any pin mode. This way, they can always monitor a pin without dictating mode. Also, I would like to increase the number of integrators to 15, each differentiated in some way, like you've shown. That way, we can get 4 bits per clock, instead of one. I wish I could work on that right now.
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