P2 chip status

I'm afraid to ask, but I didn't see a sticky or anything on it..

What's the latest status on getting a P2 chip? Real silicon, that I can buy from Parallax? Not interested in the FPGA testing phase, just would like to know when a chip will be available.

Late this year?
Next year?
It's never going to happen, use the FPGA files and roll your own?

What's up. Please don't rip me a new one for asking - I just couldn't find an answer searching the forum or wiki or anywhere.

Go.

Comments

  • JRetSapDoogJRetSapDoog Posts: 853
    edited 2016-01-28 (7:50 PM)
    Chip gave this response to a similar question in the "Propeller 2 Specs" thread on Jan 7th, 2016:
    cgracey wrote: »
    tryit wrote: »
    Back to the original thread topic, at the rate of progress of the prop 2, can we expect a finished product by end of 2016? 2017? If you wait too long, can it become obsolete at the current rate of technology?

    I think 2016 is quite certain.

    In some ways it will be obsolete ten years ago, but in others it will be cutting edge ten years from now. It's a paradox.

    Parallax has also initiated a build of 20 more FPGA boards for testing. Of course, no attempt at final silicon will be made without considerable testing on these and other boards. And Chip is getting really close to releasing an FPGA image that includes the smart pin logic (for the first time). Such a release will be a major milestone on the path to silicon (no real planning can happen before that takes place).

    It'd be great if a silicon release could happen this year. But the finalization process (fine-tuning the chip) will likely take some time. And there's always the risk that feature-creep will push things back. As such, I kind of feel that silicon won't happen in 2016 UNLESS there's a concerted effort by Parallax to schedule the remaining design phases out, putting some soft deadlines in place (though it seems unlikely that any scheduling decisions will be made until after an FPGA release is issued with the smart pin logic). But the problem with implementing a schedule is that unforeseen problems could crop up. Worse, such a schedule could seriously crimp Chip's design process, resulting in a chip not as capable and simple as he/we would like it to be. But Chip seems quite pleased with the recent progress and the current design. He's very familiar with the tools and design flow now and a lot of the critical design decisions have already been made, making it easier to focus on the final details. So progress is happening at a good clip. Based on his comments, it looks like we're headed towards a great chip towards the end of this year or the first half of next year. I hope its this year if such a timeframe doesn't compromise things (which I doubt Parallax would let happen). Anyway, once the next FPGA release comes out, I think it will be reasonable for us to start getting giddy (chomping at the bit), but probably not before.
  • We haven't really begun proper testing in FPGA yet. Likely to be in the next week(s).
    IMHO, the earliest we are likely to see a chip in the flesh is later this year.
  • jmgjmg Posts: 14,572
    fixmax wrote: »
    Not interested in the FPGA testing phase, just would like to know when a chip will be available.
    You should be interested in the FPGA testing phase, as that has to be done before the design moves to silicon.
    Production volumes I would place in 2017, but the data/specs will be available likely this quarter.
    That means you can start designs, and even do a hybrid design that uses a CPLD/FPGA, with an eye to P2 migrate just as your volumes build.

  • jmg wrote: »
    That means you can start designs, and even do a hybrid design that uses a CPLD/FPGA, with an eye to P2 migrate just as your volumes build.

    As long as the design stays locked down once once the 'final' FPGA image is released.
  • jmgjmg Posts: 14,572
    jmg wrote: »
    That means you can start designs, and even do a hybrid design that uses a CPLD/FPGA, with an eye to P2 migrate just as your volumes build.

    As long as the design stays locked down once once the 'final' FPGA image is released.

    Of course, but I'm not sure of your point, as Parallax will certainly strive to have the testing code, not differ from the FAB code.
    That's the whole point of testing in FPGAs.

    There are also many solutions when using a CPLD/FPGA - an interim design does not even have to run P2 COGS, if you want to use the Smart Pins features for example.
  • jmg wrote: »
    jmg wrote: »
    That means you can start designs, and even do a hybrid design that uses a CPLD/FPGA, with an eye to P2 migrate just as your volumes build.

    As long as the design stays locked down once once the 'final' FPGA image is released.

    Of course, but I'm not sure of your point, as Parallax will certainly strive to have the testing code, not differ from the FAB code.
    That's the whole point of testing in FPGAs.

    There are also many solutions when using a CPLD/FPGA - an interim design does not even have to run P2 COGS, if you want to use the Smart Pins features for example.
    Did I miss something here? Is Parallax planning to release the Verilog for P2 prior to silicon being available? If not, I don't see how you can use CPLD/FPGA with smart pins without the rest of P2. I suppose you could build a product around one of the FPGA boards that Parallax intends to support but that would probably not be just a bare smart pin attached to P1v or something like that.

  • jmgjmg Posts: 14,572
    David Betz wrote: »
    Did I miss something here? Is Parallax planning to release the Verilog for P2 prior to silicon being available? If not, I don't see how you can use CPLD/FPGA with smart pins without the rest of P2. I suppose you could build a product around one of the FPGA boards that Parallax intends to support but that would probably not be just a bare smart pin attached to P1v or something like that.

    Even if the Verilog is not released, the Specs will be, and those specs can be used to create 'same interface' pin operation that the product needs.
    You do not need to emulate all the corner cases, just have it register-compatible for setup and operation in the designs particular use.

    Given Parallax are keen to get testing coverage, adding a P2 Pin-cell to P1V (ie release the Verilog) seems a smart way to expand testing coverage significantly - but that is their call.
    First they will release it as part of P2 bit stream.

  • I wonder if Parallax could release various parts of P2 (COG, SmartPin, etc) as "hard macros"? That way they protect their IP but people can integrate P2 blocks into their designs. Maybe even something like the stripped down versions that Chip currently provides for the DE0-Nano with only a single COG.
  • I'd like to see some function block diagrams like the counters for the Prop1. There is lots of places where that'd help instructionally for understanding the Prop2 ... and educationally for processor architecture.

    I like the quote, "A picture is worth a thousand words." Although, labelling the diagrams always helps too. :D
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