Thinking some more....
If the pipeline is 2 stage? then surely one space instruction is enough.
The results from the P123-A7 (Cyclone V) were ~95% correct with one spacer.
I feel their may still be something else going on here.
Perhaps Chip can shine some light on this.
Chip used to have a timing diagram in his earlier instructions.txt files that showed when the instructions are fetched, and when the results are written. I can't find the timing diagram right now, but I believe that the instruction is being written at the same time it is being fetched when there is only one NOP. If so, this would require a mux that would use the value being written for the fetched instruction when the cog addresses match. If this mux doesn't exist then the value that is fetched would depend on the characteristics of the RAM in the FPGA. Maybe one version of the FPGA chip works without the mux, and the other version doesn't.
Thinking some more....
If the pipeline is 2 stage? then surely one space instruction is enough.
The results from the P123-A7 (Cyclone V) were ~95% correct with one spacer.
I feel their may still be something else going on here.
Perhaps Chip can shine some light on this.
Chip used to have a timing diagram in his earlier instructions.txt files that showed when the instructions are fetched, and when the results are written. I can't find the timing diagram right now, but I believe that the instruction is being written at the same time it is being fetched when there is only one NOP. If so, this would require a mux that would use the value being written for the fetched instruction when the cog addresses match. If this mux doesn't exist then the value that is fetched would depend on the characteristics of the RAM in the FPGA. Maybe one version of the FPGA chip works without the mux, and the other version doesn't.
the result from the SETS is written in the same cycle that the MOV instruction is being fetched. This either requires that the RAM passes through the value as it is being written or there has to be a mux that will pass the value through when the read and write addresses match.
It seems like this issue may have fallen between the cracks. So when modifying an instruction, are two spacer instructions required, or is one supposed to be sufficient?
Perhaps ALTI can be renamed to ALTNEXT or ALTNXT, so it does not suggest a specific field.
Regarding differencies for Cyclone 4 and 5:
Maybe the dual ported RAM behaves differently on read while write. Some FPGAs read the new value written and some return the old value when the same address is written and read.
Andy
That's the only place where a difference could exist, read during write.
Does the DE2-115 always work with one spacer instruction?
I had set the read-during-write behavior to 'don't care' on the Cyclone V builds. I can set it to read=write, but I really need to find out what the OnSemi RAMs will do.
Comments
It will be a little strange using two different instructions depending on how far away the destination is.
Sorry if it's too wide for your screen. Zoom out or copy and paste it somewhere else.
The result of an instruction is written at the same time the second instruction after it is fetched.
That's the only place where a difference could exist, read during write.
Does the DE2-115 always work with one spacer instruction?