Error in Elements of Digital Logic?

In the Elements of Digital Logic book p. 75, the clocked RS latch has NOR gates in the drawing but the accompanying text indicates that it should be NAND gates. Would someone clarify this for me?

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  • edited December 2004 Posts: 0Vote Up0Vote Down
    Hi there,
    You have found an error in the book. I believe that is the most significant one in Version 1.0. The diagram is correct and the text describing the diagram is incorrect. You can construct the RS Latch with either NAND or NOR Gates. Which one you use depends on the type of input used. the book was originally written to use NAND Gates. Working through the text showed us that using NOR Gates was the correct method rather than NAND Gates. The images were promptly changed, but the text was overlooked. Please accept my apology.
    We learned this soon after v1.0 was published and created an errata for it. I just checked our website to find a URL for you and found that the webmaster has replaced it with a link to a PDF of the revised text.
    www.parallax.com/dl/docs/books/edu/EoDL_v1.0a.pdf
    If you have any other issues, comments, or questions, feel free to email directly: jbarrowman@parallax.com

    Kind Regards,

    John Barrowman
    Engineering
    Parallax, Inc.
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