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  • Publison wrote: »

    Sounds interesting. However... The one from IBM, well I did meet the originator behind their code that they are releasing for the BlueGene system.

    Oddly enough the Google idea was brought up inside Hack A Day not all that long ago. Let's just say the gang inside there wasn't thrilled with it.
  • At 130 nm, can we get a P1V with 512K HUB, 2K COG RAM, 16 cogs? Only 100 items per customer.
  • Publison wrote: »
    At 130 nm, can we get a P1V with 512K HUB, 2K COG RAM, 16 cogs? Only 100 items per customer.
    Nice! Who's going to submit it?

  • Publison wrote: »
    At 130 nm, can we get a P1V with 512K HUB, 2K COG RAM, 16 cogs? Only 100 items per customer.

    Has to fit in 10 mm2, is the key detail missing there. The prop2 has 7x that area at 180 nm. 512 kB of SRAM would take all the 10 mm2 at 130 nm I suspect.

  • P1 with 64K Hub and at 130nm fab probably running about 250 MHz could be an interesting beast.
  • localroger wrote: »
    P1 with 64K Hub and at 130nm fab probably running about 250 MHz could be an interesting beast.
    Yes, and with all 64 I/O perhaps. This is what we always wanted as a easy upgrade path in the beginning. P2 is great for sure, but a better P1 is also great in its own way.

  • evanhevanh Posts: 9,702
    edited 2020-07-05 - 03:00:59
    Here's one of those inflection points in the history of the prop2 that's helpful for estimating what can fit - http://forums.parallax.com/discussion/167451/logic-too-big

    And some numbers from 18 months earlier - http://forums.parallax.com/discussion/comment/1371876/#Comment_1371876

  • Cluso99Cluso99 Posts: 16,392
    edited 2020-07-05 - 03:10:43
    IIRC the P2 is 8.5x8.5mm = ~72mm2 so about 38mm2 at 130nm. Not going to fit!

    With only 10mm2 there isn't going to be much space for I/O pins so 32 would likely be the max if even possible.

    But a 64KB hub ram P1 with the few helper instructions to execute LMM or even hubexec would be nice indeed. Remember, the P1 has a 16 slot hub cycle so even making it 8 slots would double hub speed and should be doable. May be enough space to use dual-port cog ram and you'd get 2 clocks instead of 4 per instruction. And say 400MHz too. A P1 compatible on steroids :)

    The PLLs are the main P1 problem here :(
  • Cluso,
    My post isn't about the prop2 at all.

  • Cluso99 wrote: »
    The PLLs are the main P1 problem here :(

    The article spoke of an open-source PDK that included analog models. One would expect some sort of clock multiplier function even if it doesn't offer the flexibility of the PLL in the P1.
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