smartpin SPI (bidirectional) sample code?

Had a bit of a search but didn't find anything obvious, I'm sure someone has some examples of this to avoid re-inventing the wheel?

Comments

  • As in single data pin, or just using both DI and DO in conversation?
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  • Cluso will have routines in the ROM monitor for talking with SPI Flash chips.
    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • In the ROM monitor there are three vesrions of SPI code...
    Chips booter which accesses the FLASH. He uses separate send and receive routines.
    My SD booter which uses a combine send/receive routine with various entry points depending on what you are needing to do. Easiest way, search for the label SENDFF.
    Peters TAQOZ. YOu will have to ask Peter.
    My Prop boards: P8XBlade2 , RamBlade , CpuBlade , TriBlade
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    Website: www.clusos.com
    P1: Tools (Index) , Emulators (Index) , ZiCog (Z80)
    P2: Tools & Code , Tricks & Traps
  • Mark_TMark_T Posts: 1,981
    edited 2019-02-27 - 15:16:18
    I think all the ROM monitor booter stuff is bitbanged, not smartpin.
  • Yes. Didn’t realise you wanted smartpins mode.
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  • Well it seems like a thing that smartpins should be doing (if only to make the clock speed easily configurable).
    But bit bashing is useful too :)
  • jmgjmg Posts: 14,142
    Mark_T wrote: »
    Well it seems like a thing that smartpins should be doing (if only to make the clock speed easily configurable).
    But bit bashing is useful too :)

    Smart pins are used in the UART side, because highest baud rate helps there, and the buffering buys time to allow SPI bit-bash.
    I think one reason to KISS on SPI was to keep the boot silicon minimal, and so lower the risk of smart pin flaws causing dead-in-water outcomes...
  • It'd be interesting to see if using Smartpin + Interrupt would let you juggle several I/O things in one cog.

    Things like SPI and I2C and serial are so slow compared to P2 clock speed, seems very doable...
    Prop Info and Apps: http://www.rayslogic.com/
  • I have a two port async-serial driver with buffers in LUT using smart pins and interrupts. The smart pins easy outrun the HUB/LUT transfer, with up to sys clock baud, without issues. not sure to what to connect with 180Mbaud, but the pins work and the interrupts do also.

    That speed also outruns my Scope, so no pictures...

    Enjoy!

    Mike
    I am just another Code Monkey.
    A determined coder can write COBOL programs in any language. -- Author unknown.
    Press any key to continue, any other key to quit

    The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT", "SHOULD", "SHOULD NOT", "RECOMMENDED", "MAY", and "OPTIONAL" in this post are to be interpreted as described in RFC 2119.
  • Nice :smiley:

    180Mbaud = 180bps = 18MB/s

    We can write to hub at 4Bytes/clock for a block using wrlong and setq (plus setup), so 4B @ say 180MHz = 720MB/s
    My Prop boards: P8XBlade2 , RamBlade , CpuBlade , TriBlade
    P1 Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
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  • Rayman wrote: »
    It'd be interesting to see if using Smartpin + Interrupt would let you juggle several I/O things in one cog.

    Things like SPI and I2C and serial are so slow compared to P2 clock speed, seems very doable...

    Well there are some pretty high SPI clock rates out there, 40MHz and up...
  • Cluso99 wrote: »
    Nice :smiley:

    180Mbaud = 180bps = 18MB/s

    We can write to hub at 4Bytes/clock for a block using wrlong and setq (plus setup), so 4B @ say 180MHz = 720MB/s

    Yes, I tried and failed. I have the data in longs in the LUT but failed over days to get my buffers running with long transfers to/from HUB.

    Finally I gave up, just transfer Bytes from HUB to LUT and vice versa, shortend everything up and made space to include decimal, hex output and string input into the COG.

    I need to check the new printf stuff in spin2gui/fastspin to maybe include that also to be compatible with them existing drivers.

    Weekend is coming...

    Enjoy!

    Mike
    I am just another Code Monkey.
    A determined coder can write COBOL programs in any language. -- Author unknown.
    Press any key to continue, any other key to quit

    The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT", "SHOULD", "SHOULD NOT", "RECOMMENDED", "MAY", and "OPTIONAL" in this post are to be interpreted as described in RFC 2119.
  • FredBlaisFredBlais Posts: 368
    edited 2019-03-03 - 16:50:38
    ***UPDATED 2***
    final code in TAQOZ thread

    ***UPDATED***

    Here is some TAQOZ smartpin SPI code (only output for now)
    input working, tested with MISO looped back with MOSI with a jumper
    and MISO looped back internally with MOSI via 'a' input selector relative pin -1 (see commented out code)
    ( 300MHZ 3.3ns PER CLOCK 10000 = 33.3us )
    8 := CLK
    9 := MOSI
    10 := MISO
    11 := SS
    15000 := FREQ
    CLKHZ FREQ / := N_PULSES
    
    : CPOL0_CPHA0
    CLK PIN %0000_0_0_0_000_000 8 << %1_00100_0 OR WRPIN
    N_PULSES 2/ 16 << N_PULSES OR WXPIN L
    MOSI PIN %0000_0111_000_0000_000_000_000 8 << %01_11100_0 OR WRPIN %101000 WXPIN
    MISO PIN %0111_1110_000_0000_000_111_111 8 << %01_11101_0 OR WRPIN %100111 WXPIN
    \ MISO PIN %0000_1110_000_0000_000_111_111 8 << %01_11101_0 OR WRPIN %100111 WXPIN
    ;
    
    : CPOL1_CPHA1
    CLK PIN %0000_0_0_1_000_000 8 << %1_00100_0 OR WRPIN
    N_PULSES 2/ 16 << N_PULSES OR WXPIN L
    MOSI PIN %0000_1111_000_0000_000_000_000 8 << %01_11100_0 OR WRPIN %101000 WXPIN
    MISO PIN %0111_0110_000_0000_000_111_111 8 << %01_11101_0 OR WRPIN %100111 WXPIN
    \ MISO PIN %0000_0110_000_0000_000_111_111 8 << %01_11101_0 OR WRPIN %100111 WXPIN
    ;
    
    : SEND ( TX_BYTE -- RX_BYTE )
    SS PIN L 
    MOSI PIN F REV 23 >> WYPIN L
    MISO PIN L
    CLK PIN 8 WYPIN WAITPIN
    MOSI PIN F
    SS PIN H
    MISO PIN RDPIN F REV
    ;
    

    Sample
    CPOL1_CPHA1
    TAQOZ# $00 SEND .BYTE --- 00 ok
    TAQOZ# $FF SEND .BYTE --- FF ok
    TAQOZ# $AA SEND .BYTE --- AA ok
    TAQOZ# $11 SEND .BYTE --- 11 ok
    
    BK00002.BMP
    BK00004.BMP
    BK00005.BMP
    BK00006.BMP
    CPOL0_CPHA0
    TAQOZ# $00 SEND .BYTE --- 00 ok
    TAQOZ# $FF SEND .BYTE --- FF ok
    TAQOZ# $AA SEND .BYTE --- AA ok
    TAQOZ# $11 SEND .BYTE --- 11 ok
    
    BK00007.BMP
    BK00008.BMP
    BK00009.BMP
    BK00010.BMP
    SPI_timing.png
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