List of Changes in Next P2 Silicon

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  • Wendy says that the final tapeout paperwork will be done today, so the fabrication can begin.
  • cgracey wrote: »
    Wendy says that the final tapeout paperwork will be done today, so the fabrication can begin.

    LET THE FABRICATION BEGIN!!

    Just had to type that. Not sure why. Go, dog, go!

    KG
  • Excellent news Chip!
    Thanks for the update. Going to be a good summer, I think.
  • PublisonPublison Posts: 11,060
    edited 2019-04-02 - 19:07:59
    Good News!
    In addition to the P2-ES boards, are there going to be a few chips available from this run to populate our P2D2 boards?
  • YanomaniYanomani Posts: 885
    edited 2019-04-02 - 18:52:19
    Oh Chip, these are excellent news!!!

    More than 1/3 of power dissipation figures did flew away. Awesome magic!

    And without having to recur to any sort of assisted cooling.

    Perhaps, now is the right moment to ask Wendy, so she has time to substitute those two chinese guys, the ones that were riding alligators, by two Inuits, happilly feeding some penguins? :lol:

    It's just a pity OnSemi didn't has any crystal-clear, thermally-enhanced globe-topping compound available, that passed their caracterization/quality screening, to surround the whole cake.
  • cgracey wrote: »
    Wendy says that the final tapeout paperwork will be done today, so the fabrication can begin.
    That sounds great! Congratulations! I guess we'll have final P2 chips soon. At least, I hope this is the last spin before production.

  • I'm looking forward to the HDMI feature.
    The max. clock frequency is probably limited by something other than heat, right?
    Prop Info and Apps: http://www.rayslogic.com/
  • jmgjmg Posts: 14,094
    cgracey wrote: »
    Wendy sent me the power reports for the download test (1 cog at 20MHz) and the power torture test, where all 8 cogs are executing from hub and all 64 smart pins are running PWM at a clock frequency of 182MHz:
    And here's the power torture test. The old silicon dissipated 1.2W, while the new silicon will dissipate 790mW:

    Looking good. With pretty much the same silicon active, in the everything running case, what has made this lower power ?

  • jmg wrote: »
    cgracey wrote: »
    Wendy sent me the power reports for the download test (1 cog at 20MHz) and the power torture test, where all 8 cogs are executing from hub and all 64 smart pins are running PWM at a clock frequency of 182MHz:
    And here's the power torture test. The old silicon dissipated 1.2W, while the new silicon will dissipate 790mW:

    Looking good. With pretty much the same silicon active, in the everything running case, what has made this lower power ?

    Clock gating has reduced the power. This design even has 15% more logic than the current silicon.
  • Rayman wrote: »
    I'm looking forward to the HDMI feature.
    The max. clock frequency is probably limited by something other than heat, right?

    Well, aside from temperature, there are process conditions, which are fixed per die, and then there's voltage level.
  • jmgjmg Posts: 14,094
    cgracey wrote: »
    Clock gating has reduced the power. This design even has 15% more logic than the current silicon.
    That makes sense for 1 COG, but where you test all 8 cogs are executing from hub and all 64 smart pins are running PWM at a clock frequency of 182MHz: what is not being used & so is gated off ?
    I think Cordic is disabled in that test ? What else is gated off to save power ?

  • It's really good to read that power has reduced by a third in the torture test, Chip. That alone seems worth it, and all portable battery powered P2 applications have just gained more runtime - almost up to 50% more in the most extreme cases where all power goes to the P2 and it's running flat out. Also board design currents are now lowered and resistive losses in power inductors will be a lot less. I like it a lot.
  • Fantastic news Chip :smiley:

    ~30% power reduction for full operation is a really nice achievement - and don't forget you added quite a bit of logic too.
    My Prop boards: P8XBlade2 , RamBlade , CpuBlade , TriBlade
    P1 Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
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    P1: Tools (Index) , Emulators (Index) , ZiCog (Z80)
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  • cgracey wrote: »
    Wendy sent me the power reports for the download test (1 cog at 20MHz) and the power torture test, where all 8 cogs are executing from hub and all 64 smart pins are running PWM at a clock frequency of 182MHz:

    Here is the download power test. This is how much power will be dissipated when the chip is waiting for a download or actively downloading, where one cog is active. The current silicon dissipates 136mW, while the new silicon will dissipate 75mW:
    ****************************************
    Report : Averaged Power
    Design : CHIP
    Version: M-2016.12-SP1
    Date   : Fri Mar 29 12:07:38 2019
    ****************************************
    
                            Internal  Switching  Leakage    Total
    Power Group             Power     Power      Power      Power   (     %)  Attrs
    --------------------------------------------------------------------------------
    clock_network              0.0292    0.0154 3.322e-06    0.0446 (59.10%)  i
    register                3.302e-03 1.622e-04 2.591e-05 3.490e-03 ( 4.63%)  
    combinational           7.393e-03    0.0132 7.511e-05    0.0207 (27.44%)  
    sequential              3.650e-04 3.531e-06 1.264e-06 3.698e-04 ( 0.49%)  
    memory                  1.819e-03 1.972e-03 1.950e-04 3.986e-03 ( 5.28%)  
    io_pad                     0.0000 2.225e-03 8.824e-05 2.313e-03 ( 3.07%)  
    black_box                  0.0000    0.0000 9.160e-14 9.160e-14 ( 0.00%)  
    
      Net Switching Power  =    0.0330   (43.72%)
      Cell Internal Power  =    0.0421   (55.77%)
      Cell Leakage Power   = 3.889e-04   ( 0.52%)
                             ---------
    Total Power            =    0.0754  (100.00%)
    

    And here's the power torture test. The old silicon dissipated 1.2W, while the new silicon will dissipate 790mW:
    ****************************************
    Report : Averaged Power
    Design : CHIP
    Version: M-2016.12-SP1
    Date   : Thu Mar 28 12:17:02 2019
    ****************************************
    
                            Internal  Switching  Leakage    Total
    Power Group             Power     Power      Power      Power   (     %)  Attrs
    --------------------------------------------------------------------------------
    clock_network              0.3084    0.1488 3.312e-06    0.4572 (57.93%)  i
    register                8.300e-03 3.107e-03 2.573e-05    0.0114 ( 1.45%)  
    combinational              0.0361    0.0769 7.545e-05    0.1131 (14.33%)  
    sequential              4.566e-04 2.212e-05 1.270e-06 4.800e-04 ( 0.06%)  
    memory                     0.1056 1.972e-03 1.950e-04    0.1078 (13.65%)  
    io_pad                     0.0000    0.0992 8.938e-05    0.0993 (12.58%)  
    black_box                  0.0000    0.0000 9.151e-14 9.151e-14 ( 0.00%)  
    
      Net Switching Power  =    0.3301   (41.82%)
      Cell Internal Power  =    0.4589   (58.13%)
      Cell Leakage Power   = 3.902e-04   ( 0.05%)
                             ---------
    Total Power            =    0.7894  (100.00%)
    

    Note that these power figures are for CORE logic and memory, and do not include the 3.3V I/O pads.
    This is quite a big improvement, and we have to take into account that the current P2 prototype already gets warm and not hot while using all its cogs to calculate big prime numbers at 160MHz. Never measured the power consumption on the P2 eval board while doing this, but that might be on the works.

    I'm expecting the final P2 to be very stable and quite overclockable, just by seeing this trend. Probably, one can expect to see a less jittery VGA output, judging by the simulations of this new iteration.

    Kind regards, Samuel Lourenço
  • jmg wrote: »
    cgracey wrote: »
    Clock gating has reduced the power. This design even has 15% more logic than the current silicon.
    That makes sense for 1 COG, but where you test all 8 cogs are executing from hub and all 64 smart pins are running PWM at a clock frequency of 182MHz: what is not being used & so is gated off ?
    I think Cordic is disabled in that test ? What else is gated off to save power ?

    CORDIC commands are being issued, also. I forgot about that.
  • jmgjmg Posts: 14,094
    cgracey wrote: »
    CORDIC commands are being issued, also. I forgot about that.
    So what is not running on that test, that was before, or is the layout and routing now inherently lower power ?

    P2es models to have this Cpd Cpd=1.60nF+8*83.33pF/COG

    If I assume that boot test was at the typical 23MHz that gives
    Fi=23M Icc=41.9m
    Cpd=((Icc)*Vcc)/(Vcc*Vcc*Fi)
    Cpd = 1.012nF

    Fi=182M Icc=438.5m
    Cpd=((Icc)*Vcc)/(Vcc*Vcc*Fi)
    Cpd = 1.338nF

    Difference / 8 gives 40.805pF/(COG+8 smart pins)
    P2+ then has Cpd ~ 1.012nF + 40.805pF/(COG+8 smart pins)

    At 20kHz RCSLOW, that indicates Cpd contribution of ~ 36uA (+ RCSLOW Icc + Static Leakage)
  • Cluso99Cluso99 Posts: 15,531
    edited 2019-04-03 - 02:09:01
    I am interested to know what the max freq might be for lower specs like commercial temp 0-70C and 5% Vcc?
    My Prop boards: P8XBlade2 , RamBlade , CpuBlade , TriBlade
    P1 Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
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    P1: Tools (Index) , Emulators (Index) , ZiCog (Z80)
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  • jmgjmg Posts: 14,094
    Cluso99 wrote: »
    I am more interested to know what the max freq might be for lower specs like commercial temp 0-70C and 5% Vcc.

    That will likely need bench tests on real silicon to get a typical, but the better numbers simulated here, means it should come in better than the existing P2es, as the die temperature is lower.
    Maybe even 3% or 2% Vcc spec is viable ?
  • jmg wrote: »
    Cluso99 wrote: »
    I am more interested to know what the max freq might be for lower specs like commercial temp 0-70C and 5% Vcc.

    That will likely need bench tests on real silicon to get a typical, but the better numbers simulated here, means it should come in better than the existing P2es, as the die temperature is lower.
    Maybe even 3% or 2% Vcc spec is viable ?
    No. It’s not a typical value.
    It’s a tools value and yes it could be 2.5% Vcc.
    It would be a value OnSemi eould calculate from the tools. These days you often get multiple specs.
    My Prop boards: P8XBlade2 , RamBlade , CpuBlade , TriBlade
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    P2: Tools & Code , Tricks & Traps
  • Chip,
    Was there such data for the P2ES chip? It would be nice to compare.
    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • cgraceycgracey Posts: 11,900
    edited 2019-04-03 - 06:21:36
    evanh wrote: »
    Chip,
    Was there such data for the P2ES chip? It would be nice to compare.

    Here is the power torture test from the first silicon:
    ****************************************
    Report : Time Based Power
    Design : CHIP
    Version: M-2016.12-SP1
    Date   : Tue Jun 19 13:00:59 2018
    ****************************************
    
                            Internal  Switching  Leakage    Total
    Power Group             Power     Power      Power      Power   (     %)  Attrs
    --------------------------------------------------------------------------------
    clock_network              1.0062    0.2775 3.036e-07    1.2836 (61.15%)  i
    register                   0.0192    0.0135 6.570e-06    0.0327 ( 1.56%)  
    combinational              0.1635    0.2312 2.367e-05    0.3947 (18.81%)  
    sequential              2.048e-03    0.0000 2.911e-07 2.048e-03 ( 0.10%)  
    memory                     0.3495    0.0120 9.432e-05    0.3616 (17.23%)  
    io_pad                     0.0000    0.0242 8.556e-05    0.0243 ( 1.16%)  
    black_box                  0.0000    0.0000 8.431e-15 8.431e-15 ( 0.00%)  
    
      Net Switching Power  =    0.5584   (26.60%)
      Cell Internal Power  =    1.5403   (73.39%)
      Cell Leakage Power   = 2.107e-04   ( 0.01%)
                             ---------
    Total Power            =    2.0990  (100.00%)
    

    This shows 2.1W. I thought it was 1.2W.
  • evanhevanh Posts: 8,261
    edited 2019-04-03 - 07:05:29
    Thanks,
    What was wrong that gave 2.1 Watts? Should the numbers be scaled down?

    Certainly some surprising absolute differences between the two:
    - Cell Leakage Power is almost doubled now. (The transistor count can't have increased that much.)
    - Black_box is >10x bigger now! (I have no idea what this is.)
    - Io_pad is 4x bigger now. (Different inclusion prameter I presume.)

    All the others have dropped significantly, which is expected due to the clock-gating.

    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • jmgjmg Posts: 14,094
    cgracey wrote: »
    evanh wrote: »
    Chip,
    Was there such data for the P2ES chip? It would be nice to compare.

    Here is the power torture test from the first silicon:
    This shows 2.1W. I thought it was 1.2W.

    Was that the same test conditions ? - ie 8 COGS + Cordic+64 Smart Pins 182MHz PWM ?

    A direct compare is surprising
                              Total  P2+         Total   P2es
    Power Group               Power   (     %)   Power   (     %)  
    --------------------------------------------
    clock_network              0.4572 (57.93%)     1.2836 (61.15%)  i
    register                   0.0114 ( 1.45%)     0.0327 ( 1.56%)  
    combinational              0.1131 (14.33%)     0.3947 (18.81%)  
    sequential              4.800e-04 ( 0.06%)  2.048e-03 ( 0.10%)  
    memory                     0.1078 (13.65%)     0.3616 (17.23%)  
    io_pad                     0.0993 (12.58%)     0.0243 ( 1.16%)  
    black_box               9.151e-14 ( 0.00%)  8.431e-15 ( 0.00%)  
    
      Net Switching Power  =    0.3301   (41.82%)   =    0.5584   (26.60%)
      Cell Internal Power  =    0.4589   (58.13%)   =    1.5403   (73.39%)
      Cell Leakage Power   = 3.902e-04   ( 0.05%)   = 2.107e-04   ( 0.01%)
                             ---------                ---------
    Total Power            =    0.7894  (100.00%)   =    2.0990  (100.00%)
    
    There are big shifts, seems either test conditions changed, or OnSemi have revised their models ?
  • cgraceycgracey Posts: 11,900
    edited 2019-04-03 - 07:38:58
    I think that earlier silicon test must have been worst-case power (low Vt & high leakage, low temp, high Vdd). Not sure what the black-box difference is about.

    The power test results from the new silicon are at typical case.
  • The leakage is much lower in the ES data.
    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • evanh wrote: »
    The leakage is much lower in the ES data.
    evanh wrote: »
    The leakage is much lower in the ES data.

    Yeah, that doesn't make sense.

    I will ask Wendy tomorrow if she has the report that showed 1.2W for the original silicon.
  • Okay, that 2.1W power test result was for a simulation of 20% of the flops toggling on every clock, without any specific test program running. It was some kind of estimation the tools made on their own.

    Wendy is looking for the 1.2W report that was a product of running our power torture test code. When and if she finds it, I will post it here.
  • cgracey wrote: »
    Wendy reminded me yesterday that timing closure for the new P2 is set from -55C to +150C junction temperature. Our package Tja is ~20C/W. The anticipated power dissipation was ~2.25W. This would result in a ~45C (20×2.25) rise in junction temperature over ambient temperature, which affords us a -55C to +85C packaged temperature range with ~20C (150-45-85) allowance for local hot spots on the die.

    Chip,
    We use the P1 up to 125°C. Do you think the P2 will be able to run in an environment that hot ? Possibly at a reduced clock frequency ?

    We make test equipment, so it needs to be spec'd by Parallax that way, or we can't use it. IOW we can't take a chance on "it seems to work" etc.

    Thanks,
    Bean
  • cgraceycgracey Posts: 11,900
    edited 2019-04-03 - 14:13:08
    Bean wrote: »
    cgracey wrote: »
    Wendy reminded me yesterday that timing closure for the new P2 is set from -55C to +150C junction temperature. Our package Tja is ~20C/W. The anticipated power dissipation was ~2.25W. This would result in a ~45C (20×2.25) rise in junction temperature over ambient temperature, which affords us a -55C to +85C packaged temperature range with ~20C (150-45-85) allowance for local hot spots on the die.

    Chip,
    We use the P1 up to 125°C. Do you think the P2 will be able to run in an environment that hot ? Possibly at a reduced clock frequency ?

    We make test equipment, so it needs to be spec'd by Parallax that way, or we can't use it. IOW we can't take a chance on "it seems to work" etc.

    Thanks,
    Bean

    If you reduced the clock frequency enough to reduce the junction temperature rise, it would be okay, but I don't know how low-frequency you'd have to go. We will determine these things with ON's help soon.
  • Okay, thanks Chip.

    We are hoping for 100MHz. That would give us a nice round 10nSec measurement resolution.

    Bean
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