P2 PLL driving questions

Couple of questions I realise we don't have data on so far:-
1. If driving the P2 from an external oscillator, what amplitude is recommended? 3v3? 1v8?
2. Which supply pin is the PLL physically located closest to ?

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  • 11 Comments sorted by Date Added Votes
  • jmgjmg Posts: 12,090
    edited July 23 Vote Up0Vote Down
    Tubular wrote: »
    Couple of questions I realise we don't have data on so far:-
    1. If driving the P2 from an external oscillator, what amplitude is recommended? 3v3? 1v8?
    2. Which supply pin is the PLL physically located closest to ?

    FWIR all IO pins are in the 3v3 domain, so that means an External CMOS oscillator should be IO domain levels (typ 3v3)

    However, If your External Oscillator is a Clipped Sine out, (which you may choose for the lower Icc and better ppm ), you would select XTAL mode, and AC couple XIN to the Oscillator.

    Chip did publish some RING layout info, but normal practice would have the PLL and XTAL very close on the die, so treat those pins most carefully.
    ISTR the PLL was regulator / filtered on chip, with a 1v8 via LPF as the reference ? **
    I guess that means both 1v8 and 3v3 noise could impact PLL.


    There was this from 2 yrs ago, not sure how out-of-date that data file is....
    https://forums.parallax.com/discussion/164113/prop2-layout-viewer-try-it-out/p1

    ** Found the post about filtering 1v8 and using as regulator reference :
    https://forums.parallax.com/discussion/comment/1393527/#Comment_1393527

    One downside of locking the PLL/RCosc supplies to 1v8 core, is that the range of 1v8 is more limited - it may have been better to have the dedicated VDD_PLL pin Chip did think about.
    That could simply tie to 1v8 for common uses, and also allow a separate, clean/stable 1v8, so the Digital 1v8 can be more freely scaled for overclocking / underclocking / retention uses.'
    Retention tests could switch off PLL and change to LFOSC, then lower Vdd. LFOSC will drop as Vdd drops, but always be much slower than the core could operate at.


    I also find plots of RCFAST vs Temperature here ( claims "The 20MHz does simulate within 2% over the temp range.")
    https://forums.parallax.com/discussion/comment/1397074/#Comment_1397074
    but no tests of RFAST vs Vdd ?
  • TubularTubular Posts: 3,142
    edited July 24 Vote Up0Vote Down
    Good find jmg, that would indicate 1v8 domain
  • jmgjmg Posts: 12,090
    Tubular wrote: »
    Good find jmg, that would indicate 1v8 domain
    I think noise on both domains will find its way into the PLL, just in slightly differing ways.
    The 3v3 noise via the PSRR vs MHz curve, and the 1v8 noise, via Chip's LPF for V-ref.
    That means step-loads that change 1v8 will affect PLL/VCO, but hopefully the filtering means PLL can track those (ie not lose lock). RCFast would simply vary along the Vdd-MHz curve (not yet sighted?)
    Higher freq noise on the PLL-VIO pin would leak thru via that PSRR (Chip will know which VIO pin ?)
  • All the I/O is at 3.3V, including XI, XO, TES, and RESn.

    I'm not sure if this has been said enough, but the TES (was TESn) pin should be tied to GND. We made this change late in the chip design so that it would be more convenient to tie the pin off. GND was easy to route, but 3.3V would have been harder. This change was internal to On Semi's test circuitry. It just amounted to a pin name change on our side.

    The internal PLL and RC oscillator both run on an internally-regulated linear VDD supply that copies VDD and uses VIO_28_31 as the power source.
  • jmgjmg Posts: 12,090
    edited July 23 Vote Up0Vote Down
    cgracey wrote: »
    The internal PLL and RC oscillator both run on an internally-regulated linear VDD supply that copies VDD and uses VIO_28_31 as the power source.

    Maybe that important detail needs a name change on VIO_28_31, to include PLL ?
    Then paranoid layouts (or even cautious first pass layouts) could include a ferrite bead + decoupling on that pin, plus avoid high drive-loads on IO28_31 ?

    Did you ever run Vdd / Vcc vs MHz / kHz (typical) simulations for the RCFast / RCSlow ?
    I did not see RCSlow vs temperature go past ?

  • Peter JakackiPeter Jakacki Posts: 7,719
    edited July 23 Vote Up0Vote Down
    All my documentation and reference schematics and pcb show and state that this pin is connected to ground but I will go through them all and rename TEST to TESn TES.

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  • All my documentation and reference schematics and pcb show and state that this pin is connected to ground but I will go through them all and rename TEST to TESn TES.

    Okay. Good! Just leave the name as TEST, though. TEST will be fine.
  • cgraceycgracey Posts: 9,592
    edited July 24 Vote Up0Vote Down
    jmg wrote: »
    cgracey wrote: »
    The internal PLL and RC oscillator both run on an internally-regulated linear VDD supply that copies VDD and uses VIO_28_31 as the power source.

    Maybe that important detail needs a name change on VIO_28_31, to include PLL ?
    Then paranoid layouts (or even cautious first pass layouts) could include a ferrite bead + decoupling on that pin, plus avoid high drive-loads on IO28_31 ?

    Did you ever run Vdd / Vcc vs MHz / kHz (typical) simulations for the RCFast / RCSlow ?
    I did not see RCSlow vs temperature go past ?

    It regulates it down and has internal bypass capacitance on the regulator output. No special precaution is needed on VIO_28_31.

    I have not done any voltage-versus-speed tests on the internal RC oscillators using the actual silicon.
  • jmgjmg Posts: 12,090
    cgracey wrote: »
    It regulates it down and has internal bypass capacitance on the regulator output. No special precaution is needed on VIO_28_31.
    Do you have PSRR values - ie dB vs MHz plots for the regulator ?

  • jmg wrote: »
    cgracey wrote: »
    It regulates it down and has internal bypass capacitance on the regulator output. No special precaution is needed on VIO_28_31.
    Do you have PSRR values - ie dB vs MHz plots for the regulator ?

    No, but I SPICE simulated the design with +-0.5V noise on the VIO supply and it produced maybe 20mV of noise on the VDD-copy supply. The PLL topology has really excellent PSRR, anyway. So, I'd say the effects are negligible. I know you'd like a number, but that's all I've got.
  • jmgjmg Posts: 12,090
    cgracey wrote: »
    The internal PLL and RC oscillator both run on an internally-regulated linear VDD supply that copies VDD and uses VIO_28_31 as the power source.

    I forgot to check - I presume that VIO_28_31 also powers the XTAL Oscillator Linear unbuffered inverter stage + Internal Buffers ?
    Did a schmitt make it into the XTAL Osc post-buffer path, or is it still a simple inverter chain ?
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