P2 BOOT SEQUENCE: Serial, Flash, SD, Taqoz

2»

Comments

  • jmg wrote: »
    Seairth wrote: »
    It seems that there's still some work to be done on the new boot sequence. Assuming that it's easy to re-synthesize the ROM prior to final production, it seems that the prudent action right now would be to get the test chips made with a minimal boot ROM that provides only serial and a single external device (such as SPI flash). This would reduce the risk of unintended problems with the test chip due to rushed work, and would still allow development of the full-featured boot ROM for the production run.

    Good question. Some ROMs are designed as top-layer only changes, not sure about this OnSemi ROM ?
    It is also quite rare for chip vendors to release revision A parts to full production.

    A related question is with the lowered logic usage, from refined timing, is there room to bump the ROM to more than 16k (32k? 48k? 64k?)

    We will be able to get it right the first time, I think. OnSemi sees big expenses in changes, as it affects the overall "product program". And they don't have much bigger ROMs. I asked earlier. What we've got is about as much as is practical.
  • jmgjmg Posts: 12,092
    cgracey wrote: »
    We will be able to get it right the first time, I think. OnSemi sees big expenses in changes, as it affects the overall "product program". And they don't have much bigger ROMs. I asked earlier. What we've got is about as much as is practical.
    Fingers crossed, I guess.....

    What about Seairth's question - how many metal layers are needed to revise a ROM ?

  • jmg wrote: »
    cgracey wrote: »
    We will be able to get it right the first time, I think. OnSemi sees big expenses in changes, as it affects the overall "product program". And they don't have much bigger ROMs. I asked earlier. What we've got is about as much as is practical.
    Fingers crossed, I guess.....

    What about Seairth's question - how many metal layers are needed to revise a ROM ?

    I think just one.
  • cgracey wrote: »
    jmg wrote: »
    Seairth wrote: »
    It seems that there's still some work to be done on the new boot sequence. Assuming that it's easy to re-synthesize the ROM prior to final production, it seems that the prudent action right now would be to get the test chips made with a minimal boot ROM that provides only serial and a single external device (such as SPI flash). This would reduce the risk of unintended problems with the test chip due to rushed work, and would still allow development of the full-featured boot ROM for the production run.

    Good question. Some ROMs are designed as top-layer only changes, not sure about this OnSemi ROM ?
    It is also quite rare for chip vendors to release revision A parts to full production.

    A related question is with the lowered logic usage, from refined timing, is there room to bump the ROM to more than 16k (32k? 48k? 64k?)

    We will be able to get it right the first time, I think. OnSemi sees big expenses in changes, as it affects the overall "product program". And they don't have much bigger ROMs. I asked earlier. What we've got is about as much as is practical.
    We've waited a long time for P2 but would it make sense to delay a bit longer to have some time to test the boot ROM before it's too late? What would be the harm of pushing things back a week or to for testing?
  • jmgjmg Posts: 12,092
    David Betz wrote: »
    We've waited a long time for P2 but would it make sense to delay a bit longer to have some time to test the boot ROM before it's too late? What would be the harm of pushing things back a week or to for testing?
    I suspect that's going to happen naturally.
    It's important to not break the simple stuff, when all the more complicated stuff is bolted on...
    Question then is, when is the next OnSemi shuttle window ?

  • cgraceycgracey Posts: 9,600
    edited April 26 Vote Up0Vote Down
    jmg wrote: »
    David Betz wrote: »
    We've waited a long time for P2 but would it make sense to delay a bit longer to have some time to test the boot ROM before it's too late? What would be the harm of pushing things back a week or to for testing?
    I suspect that's going to happen naturally.
    It's important to not break the simple stuff, when all the more complicated stuff is bolted on...
    Question then is, when is the next OnSemi shuttle window ?

    OnSemi is going to run this through the fab as its own lot, with a full mask set. So, it will go to fab immediately after tape-out. No waiting for the next shuttle.
  • jmgjmg Posts: 12,092
    cgracey wrote: »
    OnSemi is going to run this through the fab as its own lot, with a full mask set. So, it will go to fab immediately after tape-out. No waiting for the next shuttle.

    Oh, wow, that's quite some project buy-in they have made there. Not too surprising, of course :)
    They must also be reasonably confident in their tools and team.
    Have they let slip their 'batting average' - ie how many done like that, that work first time ? ;)



  • Believe. Its gonna work.
    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: http://forums.parallax.com/showthread.php?123709-Commented-Graphics_Demo.spin<br>
  • cgraceycgracey Posts: 9,600
    edited April 27 Vote Up0Vote Down
    They told me that they have a 99% first-time success rate.

    Their flow is extremely thorough. I'd be surprised if it doesn't work.
  • cgracey wrote: »
    OnSemi is going to run this through the fab as its own lot, with a full mask set. So, it will go to fab immediately after tape-out. No waiting for the next shuttle.
    Wow!! Plenty of chips ;)
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
Sign In or Register to comment.