I had play with using the video generator to directly generate binary-phase-shift spread-spectrum signal.
My thought was to switch between sending $55555555 and $AAAAAAAA to the video hardware (running at 80MHz clock, so 40MHz carrier
with 2.5MHz chip-rate.
So the basic step is:
rcl chip, #1 wc
if_c mov patt, HAAAAAAAA
if_nc mov patt, H55555555
WAITVID colour, patt
With 8 instructions per chip at these rates, and waitvid taking 7 cycles minimum I think, that leaves room for 3 more instructions per chip,
allowing stepping through my 32 long chip table (1024 random bits but with zero disparity), and modulating from a bitstream at about 2.4kbaud.
I used a single long repeated as my bitstream, so about 13ms before the stream repeats, ie 76Hz or so.
Spectrum analyzer traces show the overall modulation envelope, and zoomed right in the 76Hz spaced carriers due
to the repetition rate, pretty clean (owing to the power-of-two FRQA setting of $10000000.
(I'd like to add a low-Q bandpass filter to this of course)
I've also played with baseband generation of the chips, which has the potential to be more insensitive to
PLL not being a power-of-two - the time-domain jitter ought to be less serious, allowing a receiver to vary its
PLL ratio to search for the correlation and then phase lock to the transmitter.
Using differential output PLL mode would be able to directly drive a balanced mixer for upconversion and
demodulation I think.
I've read a bit on Gold codes too, perhaps something to tie in to the chip generation.