Jordan Bunker article on the Prop2 Hack Chat from May

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Comments

  • David Betz wrote: »
    Would the smaller P2 configurations really be able to sell for significantly less than the full P2?

    There would be way less silicon and cheaper packages. So, yes.
  • I don't believe that cost is the issue. IIRc, they would have performance trade-offs such as fewer cogs - faster hub access?? or maybe not. The whole P2 thing is kinda hard for mere mortals to follow.
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  • jmgjmg Posts: 10,622
    David Betz wrote: »
    Would the smaller P2 configurations really be able to sell for significantly less than the full P2?
    Depends on your values for "significantly less".
    Certainly the price curve does not pass thru the origin, as things like testing and handling have base costs.
    The die size and package costs do change, so maybe a rough rule of thumb could be one quarter the die size might sell for half the price.

    I am impressed by the sub 35c Low Pin Count MCUs, no idea how they can package and test at those prices, but the volumes are large.
    Mickster wrote: »
    I don't believe that cost is the issue. IIRc, they would have performance trade-offs such as fewer cogs - faster hub access?? or maybe not. The whole P2 thing is kinda hard for mere mortals to follow.

    Cost is always an issue to some markets :)

    I think the eventual existence (or not) of smaller P2's, will depend on some larger customer driving the variant.
    It is certainly useful that Parallax can create differing P2 bit-files, as it allows that dialog to start.


  • BeanBean Posts: 7,814
    For our purposes chip size is the most important consideration.
    The P1 is even too big for many things.
    A scaled down P1 or P2 that would be in a 4mmx4mm (or even smaller) would be a godsend to us.
    Maybe a P1 with only 2 or 4 cogs ? and 8 I/O pins ?

    Bean
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  • jmgjmg Posts: 10,622
    Bean wrote: »
    For our purposes chip size is the most important consideration.
    The P1 is even too big for many things.
    A scaled down P1 or P2 that would be in a 4mmx4mm (or even smaller) would be a godsend to us.
    Maybe a P1 with only 2 or 4 cogs ? and 8 I/O pins ?

    Bean

    That's a tough market to play in.

    8 io pins seem to be fading, whenever I look at 8 pin or 10 pin MCUs, I always seem to come up 1-2 pins short.

    If size alone matters, did you look at the smaller FPGAs ?

    If both size and price matter, it's unlikely Parallax can compete.

    Current leading edge point I know of, for lowest price/small MCUs, is the Nuvoton N76E003.
    18kF, 1kR, UART/SPI/I2C/PWM/ADC and comes for 22c/10k in TSSOP20, or 28c in QFN20 (3x3mm)
    STC show yuan prices that suggest even less for STC8x, but that new family has an errata in some flux. Maybe 2018?


  • Bean,

    I've often thought something similar needs to exist

    One of our pcb suppliers does fine spec work, down below 3 mil track and space. On the next panel we send them I'll try a small breakout for the 81 pin Max10m08. Thats good for about 3 P1V cogs.

    For breakouts I'll use the same trick as previously dual footprinting so either a 0.1" header can be loaded, or 0.05" header which has 4x the number of pins.

  • jmgjmg Posts: 10,622
    Tubular wrote: »
    Bean,
    I've often thought something similar needs to exist

    One of our pcb suppliers does fine spec work, down below 3 mil track and space. On the next panel we send them I'll try a small breakout for the 81 pin Max10m08. Thats good for about 3 P1V cogs.
    For breakouts I'll use the same trick as previously dual footprinting so either a 0.1" header can be loaded, or 0.05" header which has 4x the number of pins.
    I see that 81p BGA comes in 56io, (4 mm, 0.4 mm pitch)

    There is also a Lattice iCE40 UltraPlus part, 5280LUT + 128KBytes RAM, comes in 30-ball WLCSP (2.15 x 2.55 mm) with 21io - maybe add that too ?

    Slightly easier to use in iCE40 UltraPlus is the QFN48, with 39io (but right now, not easy to get!)
  • Did you see A Lukats "Dipsy" module on hackaday? That was a similar size lattice

    However I think 40 or 50 IO (significantly more than a P8x32) makes it extra useful.

    Here's a pic of what I'm thinking. Nowhere near finished. Needs dual reg for that package of fpga. One advantage of the fine track breakout is its substantially single sided, so the reverse is somewhat free (though vias can't be placed in the centre)

    644 x 411 - 15K
  • jmgjmg Posts: 10,622
    Tubular wrote: »
    Did you see A Lukats "Dipsy" module on hackaday? That was a similar size lattice
    Yes, smaller FPGA tho.
    One appeal of the iCE40 UltraPlus, is the 128K bytes or SRAM
    Tubular wrote: »
    However I think 40 or 50 IO (significantly more than a P8x32) makes it extra useful.
    Yes, there is merit in going in both directions.
    Bean was asking about 8io devices, so the 21io package is ok for that end.
    Tubular wrote: »
    Here's a pic of what I'm thinking. Nowhere near finished. Needs dual reg for that package of fpga. One advantage of the fine track breakout is its substantially single sided, so the reverse is somewhat free (though vias can't be placed in the centre)
    Are there caps underneath, for better decoupling ?
    Perhaps add a footprint for an external oscillator module ? The SOT23-5 packages are cute, & easier to change.
    .. and of course, HyperRAM package next to MAX10 would be cool ;)

  • jmg,

    When the testers are running P2 files in whatever FPGA, what is the performance? e.g. something like 20% speed and twice the power consumption? Just curious theoretically, not a prop user...
    I am the Master, and technology my slave.
  • jmgjmg Posts: 10,622
    The_Master wrote: »
    jmg,

    When the testers are running P2 files in whatever FPGA, what is the performance? e.g. something like 20% speed and twice the power consumption? Just curious theoretically, not a prop user...
    Speeds are not looking too bad, they are overclocked a tad, but can be selected 60MHz and 120MHz on the latest FPGA builds (up from earlier 80MHz).
    Aspirational target for Silicon is 180MHz, but that's a broad target :)

    FPGA powers I've not seen mentioned, but they will be much higher than final silicon.

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