Jordan Bunker article on the Prop2 Hack Chat from May

cgraceycgracey Posts: 7,835
edited June 29 in Propeller 2 Vote Up1Vote Down
Hackaday just posted an article about the Hack Chat we did on May 5th:

https://hackaday.io/post/58433
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  • 41 Comments sorted by Date Added Votes
  • Chip,
    It's not targeted at any specific market, but at PEOPLE.
    Love it. There is no way out now. It has to be.
    It's nice when things work consistently, too. Today, there is a plague of flakiness that affects almost everything. The Propeller idea is to seek safe haven.
    Yep. The complexity of modern systems brings uncertainty. Flakiness. Nobody knows what is going on. Why is the instruction set manual for an ARM processor 1000 pages? It's supposed to be a RISC machine for goodness sake.




  • I do too. This has to get done. :D
    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: http://forums.parallax.com/showthread.php?123709-Commented-Graphics_Demo.spin<br>
  • Ok, that was good. But, let me do some math here...
    Parallax's investment in P2 so far has been (sounds like): CEO full time or perhaps 1/2 time for 8 (or is it 11?) years. Let's say 10 years at a miserly $200k/year. That's 2 million dollars invested.

    If it's only $~250k to complete, seems like a no brainer...
    Prop Info and Apps: http://www.rayslogic.com/
  • PS: I have to agree that Chip has made assembly very nice. I think there's no competition there...
    Prop Info and Apps: http://www.rayslogic.com/
  • It's not targeted at any specific market, but at PEOPLE.

    Pschew, I thought it might be for Martians or Dolphins. The Propeller is still a solution looking for a problem and in a parallel post here 'Who is going to buy the Propeller?' Without an answer to that and to a clear way to sell 100K in the first few years, I don't see how Parallax can justify the expense.
  • Ken GraceyKen Gracey Posts: 6,014
    edited June 30 Vote Up0Vote Down
    brucee wrote: »
    It's not targeted at any specific market, but at PEOPLE.

    Pschew, I thought it might be for Martians or Dolphins. The Propeller is still a solution looking for a problem and in a parallel post here 'Who is going to buy the Propeller?' Without an answer to that and to a clear way to sell 100K in the first few years, I don't see how Parallax can justify the expense.

    I see your point, Bruce. I guarantee you we can sell 100K chips very quickly even if we only targeted education and enthusiasts. That's not a problem.

    However, we actually need to sell 500K a year for a reasonable ROI. That takes a much more focused marketing effort and even a bit of viral adoption.

    @Rayman: don't take guesses at the cost. You're way off.

    Ken Gracey
  • @Rayman: don't take guesses at the cost. You're way off.

    Ken Gracey

    He guessed high on my salary, but didn't know about all the synthesis and layout expenses we've had over the years, mainly earlier on. We are more prudent nowadays.
  • My problem is no one has been able to spell out what the Propeller advantages are versus a cheap off the shelf micro with or without a cheap FPGA. Both cheaper than the Propeller and its assorted support circuits.

    In the education business you can use anything you want, it is a captive audience and I hope you do that well there, I'd love to see more US grown engineers.

    I get there are the hobbyists out there who want to program in assembly, but that is not the electronics market today which is dominated by time to market. Last place we were doing custom parts we rolled a new one out every 9 months and expected its life would be over in 18 months. That is the volume business, but I have also worked in the 100s to 1000s per year world where we could cobble together software from different sources, public domain or chip vendor and get something working in a matter of weeks.
  • brucee wrote: »
    My problem is no one has been able to spell out what the Propeller advantages are versus a cheap off the shelf micro with or without a cheap FPGA. Both cheaper than the Propeller and its assorted support circuits.

    In the education business you can use anything you want, it is a captive audience and I hope you do that well there, I'd love to see more US grown engineers.

    I get there are the hobbyists out there who want to program in assembly, but that is not the electronics market today which is dominated by time to market. Last place we were doing custom parts we rolled a new one out every 9 months and expected its life would be over in 18 months. That is the volume business, but I have also worked in the 100s to 1000s per year world where we could cobble together software from different sources, public domain or chip vendor and get something working in a matter of weeks.

    Our business will be many projects in the 100 to 1,000 unit range. We have no business trying to compete against off-the-shelf micros with or without a cheap FPGA.

    Ken Gracey

  • I do wonder if Parallax could make money selling a customizable FPGA solution for P1... That'd be more like a university education market, I suppose...
    Prop Info and Apps: http://www.rayslogic.com/
  • jmgjmg Posts: 10,345
    Rayman wrote: »
    I do wonder if Parallax could make money selling a customizable FPGA solution for P1... That'd be more like a university education market, I suppose...
    I wonder the same...
    There has been a trend to 'module as a product' over the last decade, plus users are more comfortable using more than one programmable device.
    This is an area Parallax should look closely at, and track as it evolves.

    I actually see three openings here, and each one has a different price point and purpose.

    At the lowest level are what I'd call Life-extenders and IO Expanders for P1.
    This can be any low-cost silicon, that can connect efficiently to a P1. eg vanilla HC595 are the lowest price, but also only one way, so is inflexible.
    I have a good candidate right now here, that can add ~40 more io lines to any P1, with a 2 pin 40~64b half duplex transport time of 18~29us.
    That is quick enough for a lot of IO tasks, and those that really do need sub-us, can connect direct to the P1 pins. It can also displace the crystal in many cases.

    Next are FPGAs that can add peripherals, and probably at least one P1V COG.

    Further up, is a FPGA able to support a meaningful portion of P2 COG/smart pin mix.

    This last opening, serves many purposes - besides being a useful module, it seeds software & resource development for P2. Do not underestimate that last bit.

  • jmgjmg Posts: 10,345
    brucee wrote: »
    ...
    I get there are the hobbyists out there who want to program in assembly, but that is not the electronics market today which is dominated by time to market. Last place we were doing custom parts we rolled a new one out every 9 months and expected its life would be over in 18 months. That is the volume business...
    That sounds like the Consumer/Fashion end of the electronics market.

    There are a lot more electronics markets than Consumer/Fashion.

    In the embedded sector, long and stable design life-cycles and support are vitally important, which is why you see the big players in this space making availability promises.
    That's something Parallax could do ?


  • Dave HeinDave Hein Posts: 5,278
    edited June 30 Vote Up0Vote Down
    Rayman wrote: »
    I do wonder if Parallax could make money selling a customizable FPGA solution for P1... That'd be more like a university education market, I suppose...
    It seems like a P1+FPGA product could be successful if the FPGA could be programmed as easily as the P1. That is, there would need to be a way to translate Spin or C into an FPGA design. Maybe something like this already exists for C -- I really don't know much about FPGA development. An IDE would need to be developed so that the user could write his code and run it on the P1+FPGA just by hitting the F10 key or from a mouse click.
  • jmgjmg Posts: 10,345
    edited June 30 Vote Up0Vote Down
    Dave Hein wrote: »
    Rayman wrote: »
    I do wonder if Parallax could make money selling a customizable FPGA solution for P1... That'd be more like a university education market, I suppose...
    It seems like a P1+FPGA product could be successful if the FPGA could be programmed as easily as the P1. That is, there would need to be a way to translate Spin or C into an FPGA design. Maybe something like this already exists for C -- I really don't know much about FPGA development. An IDE would need to be developed to all the user to just write some high level code, and then just hit F10 to program the P1 and FPGA and run the code.

    Yes, there are two parts to this...
    a) Program in the physical sense, which means to get the bit-file into SPI Flash, with least effort.
    I'm looking at the FT4222H (QuadSPI+i2c) as a 'good fit' for that, with a bonus it can also program a P1 Serial EE, giving one path for both code-files.
    (..longer term, maybe NUC505 can do FT4222H, and more.. ? )
    This memory-path-centric approach is also easier to debug, and prove, as Write and Verify do not need a working FPGA or P1.

    b) Program in the 'create the bit file' sense, that is more optional, but the educational & T&M sectors would be keen on modifying Verilog (or any FPGA HDL) and re-building.
  • Before i continue, I am sitting here overlooking Lake Tahoe with my glass of wine on a beautiful night, and I hope you all are out getting ready for a good weekend.

    The good thing is we are narrowing the question. I never thought Parallax was there for a mass market device, the ones I have worked on have been automotive, set-top box, video device, and cell phone. Yes huge markets, but never for a small player unless thye have something really novel.

    In the last few years I was part of a small design for a mom and pop business building food measuring and labeling, shipping a few thousand units a year. This was an operating small business, but they were running out of horse-power on their existing AVR based product. This device also had 2 different displays, depending on model. The one we replaced was basically a character display covering 10 different languages (in the EU). We also had to manage a couple A/Ds doing the weighing, and controlled a printer for the labeling and 3 other serial interfaces. We ended up bit-banging the one for the diagnostic unit. Another version had a full QVGA display. And a third unit had a higher rate of operation so needed a decidated A/D on a CPU.

    Sounds like a Prop could handle it all. Well not really the code to handle the character displays was over 1MB in the end and we were really pushing the limits of performance of the device. A shared hub memory or some clunky interface to an external memory would never cut it. On the QVGA display we actually were running Linux, only because it gave us access to tools to do the screens quickly and we didn't have to re-invent the wheel or pay lots of money for a video library.

    In the low volume business engineers will use what they know, which for me over the years started in the 68HC11, moved to 8051 and then to ARMs now. It will be a difficult market to penetrate without standard software tools AND libraries.
  • jmgjmg Posts: 10,345
    brucee wrote: »
    ...
    In the last few years I was part of a small design for a mom and pop business building food measuring and labeling, shipping a few thousand units a year. This was an operating small business, but they were running out of horse-power on their existing AVR based product. This device also had 2 different displays, depending on model. The one we replaced was basically a character display covering 10 different languages (in the EU). We also had to manage a couple A/Ds doing the weighing, and controlled a printer for the labeling and 3 other serial interfaces. We ended up bit-banging the one for the diagnostic unit. Another version had a full QVGA display. And a third unit had a higher rate of operation so needed a decidated A/D on a CPU.

    Sounds like a Prop could handle it all. Well not really the code to handle the character displays was over 1MB in the end and we were really pushing the limits of performance of the device. A shared hub memory or some clunky interface to an external memory would never cut it. On the QVGA display we actually were running Linux, only because it gave us access to tools to do the screens quickly and we didn't have to re-invent the wheel or pay lots of money for a video library.
    Interesting - what was the total list of MCUs each shipped system used, as they evolved ?

  • Parallax should just go into the FPGA business. A couple years back I was reading about the blurred lines between CPLD and FPGA. There was a CPLD architecture that was loaded like an FPGA. Parallax right now could design this because no flash is required.

    The article sorta talks about it being a chip for a market that doesn't exist yet. But then mentions it as an alternative to ARM.

    Just to really get crazy: Here is what I would have liked to see as someone with 20 years of embedded experience: Four 8-bit 100% deterministic 100 MIPS cores surrounded by 100 macrocell CPLD, no hubram at all. For under $10
    I am the Master, and technology my slave.
  • jmgjmg Posts: 10,345
    edited July 1 Vote Up0Vote Down
    The_Master wrote: »
    Just to really get crazy: Here is what I would have liked to see as someone with 20 years of embedded experience: Four 8-bit 100% deterministic 100 MIPS cores surrounded by 100 macrocell CPLD, no hubram at all. For under $10

    The FPGA + MCU is a market with many failures....
    Atmel did an AVR with FPGA, which failed.
    Terasic did both 8051 and ARM with FPGA, now gone...

    Even the big boys took a couple of goes at this, and only recently offer larger ARM and FPGA, that target SDRAM memory.

    A significant problem here, is the vendor has to guess and pick some locked-in-silicon combination of MCU and FPGA.
    In the Atmel AVR case, the MCU was small, but anyone wanting to use FPGA, likely needed more code space, so their achievable market was a very narrow slice.

    100 Macrocell CPLD is quite small in today's logic, and 100+ macrocell CPLDs start ~ $1.83/100 at Digikey.
  • AribaAriba Posts: 2,083
    The_Master wrote: »
    ...
    Just to really get crazy: Here is what I would have liked to see as someone with 20 years of embedded experience: Four 8-bit 100% deterministic 100 MIPS cores surrounded by 100 macrocell CPLD, no hubram at all. For under $10

    You can implement something like that on a cheap FPGA (a MAX10 for example). Simple 8bit softcores should reach 100 MIPS.
    With a bigger (but still < 10$) FPGA you can also fit 4 RISC-V cores and have a lot Logiccells free for your custom peripherals.
    The devil is in the details: How communicate the cores, how to share the ports, how many IOs, ADCs ? and how to program it (especially the logicells)?

    Andy
  • Interesting - what was the total list of MCUs each shipped system used, as they evolved ?

    I don't know which AVR was originally used, but we replaced it with an LPC4088, and later added an LPC824 dedicated to measurement. The Linux was running on some ARM9, from the days before RPi or BeagleBone.

    I think my point is that engineers will typically use what they know. These days most know and have tools for ARM, if you need more processing power add another ARM. There is such an array you can pick one with whatever peripheral you need, if you need graphics drop in a RaspPi or BeagleBone. If you need predictable timing add an FPGA, small ones are quite manageable.

    In any case learning a new proprietary language is a show stopper, and requiring assembly language is too. Time to market is key, even for small volume projects.
  • jmg wrote: »
    The_Master wrote: »
    Just to really get crazy: Here is what I would have liked to see as someone with 20 years of embedded experience: Four 8-bit 100% deterministic 100 MIPS cores surrounded by 100 macrocell CPLD, no hubram at all. For under $10

    The FPGA + MCU is a market with many failures....
    Atmel did an AVR with FPGA, which failed.
    Terasic did both 8051 and ARM with FPGA, now gone...

    Even the big boys took a couple of goes at this, and only recently offer larger ARM and FPGA, that target SDRAM memory.

    A significant problem here, is the vendor has to guess and pick some locked-in-silicon combination of MCU and FPGA.
    In the Atmel AVR case, the MCU was small, but anyone wanting to use FPGA, likely needed more code space, so their achievable market was a very narrow slice.

    100 Macrocell CPLD is quite small in today's logic, and 100+ macrocell CPLDs start ~ $1.83/100 at Digikey.

    I think part of the dilemma is that the expected programming languages for any kind of MCU+FPGA are C+Verilog/VHDL. I don't think any manufacturer would risk making anything outside of that duo template. C is for code and Verilog/VHDL is for logic. That combo, while capable, is not that great for efficiently expressing functionality. It bifurcates code and logic, right off the bat, and requires knowledge of two different disciplines. Then there's the design flow, using at least two different tools. I think that makes it kind of stinky for the customer, especially when language/IP implementations invariably differ. And going outside that HLL+HDL box is a non-starter because it defies convention. There will be no going out of the box. The box will remain and all work will be constrained within the confines of the current box paradigm - to infinity and beyond!

    I love this quote:

    “Inventions have long-since reached their limit--and I see no hope for further developments." -- Julius Frontinus, world-famous engineer (Rome, 10 AD)
  • But all that stuff goes out the window when battery power comes into play.

    I would assume this is an issue even more so today, with these amazing lithium batteries, manufacturers are still struggling with battery life.

    Do you guys have an informal estimate would percentage of propeller projects are battery powered?
    I am the Master, and technology my slave.
  • I like to think of cogs in the Propeller is kind of like an FPGA in concept. I can program them to bang pins to act like other hardware. The biggest difference being the performance/latency. Also, it's not as parallel/simultaneous as an FPGA.
    I see the P2 as taking this even further in ability.

    Here's my hope for the future of Propeller. We get the P2 done ASAP and in peoples hands, and hopefully it's a good success to fund future evolution. What I'd like to see next is just take the P2 to smaller processes so it can get a LOT more HUB memory and much higher clock rates. Imagine having the existing P2 guts, but with 16-32MB of ram or even more, and 500Mhz ot 1Ghz clockrate? Image what you could bit bang with the cogs?
  • Regarding FPGAs with processors implemented in the fabric, does anyone remember this project "The XLR8 is an FPGA board based around the Altera MAX10, implementing an ATmega-compatible microcontroller with the same program and data memory space as the ATmega328"

    It didn't seem to generate much interest. If I go to their site there are very few peripherals.

    The associated kickstarter didn't go anywhere - https://www.kickstarter.com/projects/814866572/xlr8-arduino-compatible-fpga-based-application-acc but they still released a product.
  • Here's my hope for the future of Propeller. We get the P2 done ASAP and in peoples hands, and hopefully it's a good success to fund future evolution. What I'd like to see next is just take the P2 to smaller processes so it can get a LOT more HUB memory and much higher clock rates. Imagine having the existing P2 guts, but with 16-32MB of ram or even more, and 500Mhz ot 1Ghz clockrate? Image what you could bit bang with the cogs?

    Same Roy :D

    If, somehow, we can get there? The world is wide open. This is a good vision to have, IMHO.

    I just became aware of a product design project that will be using the P1 chip. Reasons?

    Rapid development, robust operation, feature / function match, availability of necessary objects (library, code to draw from).

    P1 chips are, frankly, super easy where the tasks are within their scope of capability. BOM cost isn't a significant factor for niche / industrial designs. This dynamic is why I don't see a big problem moving the P2, once it's actualized in silicon.

    A ton of things will be super easy, P1 style, even the P1 way, SPIN + PASM. The difference on P2, is we will have the room, speed, to bring C up to that par. IMHO, it's all good on both fronts.

    ...just don't over engineer SPIN. Lean, mean + PASM is magic. No joke. Ordinary people (of which I am one) can do amazing things, quick, and don't have to know much to get it done.

    And when I say "don't have to know much", I mean it's lean enough to allow people to focus on their problem. That's where the money is, the goal is. Focus on the tools too much, and the tools become a meta problem, which is in the way of the problem.

    For those who want to pick up SPIN + PASM, it's a nice benefit.

    On P2, I'm hoping a C type environment will spring up that offers a whole lot of that same exact benefit.

    I want "the Propeller way" available to more people, and I want that for selfish reasons. Helps me, ecosystem, etc... But, it also helps them, and that's just general, good intent, type enabling tech. Always a win, when it happens.

    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: http://forums.parallax.com/showthread.php?123709-Commented-Graphics_Demo.spin<br>
  • KeithE wrote: »
    Regarding FPGAs with processors implemented in the fabric, does anyone remember this project "The XLR8 is an FPGA board based around the Altera MAX10, implementing an ATmega-compatible microcontroller with the same program and data memory space as the ATmega328"

    It didn't seem to generate much interest. If I go to their site there are very few peripherals.

    The associated kickstarter didn't go anywhere - https://www.kickstarter.com/projects/814866572/xlr8-arduino-compatible-fpga-based-application-acc but they still released a product.

    I remember it, it didn't make any sense. A under powered 8 bit mcu. Gee why not use a NIOS softcore instead? Some people don't think stuff through.

    It's also why a P1V board won't go anywhere.First off it's going to be a lot more expensive than a real Prop. Also consider this: How many FPGA based props are used in commercial/industrial goods? None as far as I know.

    A P1 and FPGA makes no sense. It sends a bad message - that the P1 can't hack it and needs muscle. May as well use a PIC32 or ARM or FPGA at that point.

    The P2 will be a bear to market. Outside of the education field along with the I&C markets, I don't see it having much of a appeal.

  • jmgjmg Posts: 10,345
    edited July 1 Vote Up0Vote Down
    rod1963 wrote: »
    A P1 and FPGA makes no sense. It sends a bad message - that the P1 can't hack it and needs muscle. May as well use a PIC32 or ARM or FPGA at that point.
    Applying that 'reasoning', all designs would be single-chip - after all, why use a USB-Bridge with a P1 ? It sends a bad message, that P1 can't hack USB, may as well use a chip that has inbuilt USB at that point.

    Of course, many DO use P1 and USB Bridges and FTDI and SiLabs and Cypress and Exar and Microchip make large numbers of parts that you'd imagine no one would really need...

    Which proves people do design with more than one chip, and they are prepared to mix chips, in a total system design approach.

    To me, it actually makes more sense to pair a Prop with a faster HS USB bridge, as that no longer limits the pairing, and lets users get more out of the Prop.
  • No mention of the P2 family. Or is this still up in the air?
    PropBASIC ROCKS!
  • Mickster wrote: »
    No mention of the P2 family. Or is this still up in the air?

    We can make all kinds of reduced-cog/RAM/pin variants. It's all governed by parameters in the top-level Verilog file.
  • Would the smaller P2 configurations really be able to sell for significantly less than the full P2?
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