• AribaAriba Posts: 2,077
    Espressif uses two Tensilica cores. Tensilica is part of Cadence Systems and in the same Business as ARM or MIPS. They may have made just the best offer.

    SiFive also wants to play in the same Business (together with about 10 other Startups for RISC-V) as Tensilica, ARM or MIPS. They all help you to produce a chip and want to see money for that.
    So why is ARM the bad guy? Just because they had the most success?

    RISC-V on FPGAs is a good alternative if you want a custom chip. As is the MICO8/MICO32 from Lattice or the NIOS2 from Altera/Intel or the Microblade from Xilinx. They all are integerated in the FPGA Toolchain and let you compound your own mix from CPU and Peripherals with some Mouseclicks.
    But FPGAs are always slower, more expensive and more power hungry than ASIC solutions.

  • I though it was a MIPS core(s).

    MIPS still have a following and the licensing is likely much cheaper than ARM can command. I read the other day that the MIPS was up for sale.
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  • TorTor Posts: 1,714
    Heater. wrote: »
    Sorry, that should have been "Espressif" core.
    Ah, thanks! That was easier to google. Found it.

  • Heater. wrote: »
    Thing is, the ESP32 has two 32 bit processors running at 240MHz with 520KB internal SRAM, 4MB FLASH, 28 GPIO, besides all it's wireless goodies.

    One wonders what the point of having the puny RISC-V implementation on the board is.

    It does not seem attractive, except for those like me that want to cheer along for open hardware and the RISC V.

    I'd be very happy if they supplied that RISC V chip on a tiny break out board.

    I'm not sure why they designed the Cinque that way either. It also has an STM32F1 IIRC for the USB stuff. The name recognition with Arduino is good for SiFive though.

    I just found this thread and have very similar interests to you @Heater. I'm excited about full open source FPGA and am interested in RISC-V design. I just ordered the RISC-V Computer Organization and Design book to get some background on cpu architecture in general.

    I actually emailed the SiFive folks and they sent me five of the E310 chips. They are the same as on the HiFive1 dev board they have and the Cinque. My guess is that the RAM will get better as they refine the chip. There is also mention of more peripherals like a second SPI that aren't brought out yet. They made it clear that the chips are engineering samples only.

    I do a lot of work with Adafruit Feather boards so I've designed a Feather with a SAMD21 for USB and the E310 to play with. Its untested because the boards are at OSH Park atm but I'm happy to post the files if folks are interested. I'd also like to put together a Feather with an ICE40 FPGA. Ideally it'd be the newer one with the QFN but I may try my hand at BGA. I'd love to get open source support for the newer chips but doubt I can find the time for reverse engineering it along with the board designs and my day job.

    Anyway, cool thread. I'd love to hear more about the status of the all open source RISC-V on FPGA.
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