P2 forum to have no moderation

Ken GraceyKen Gracey Posts: 5,859
edited February 21 in Propeller 2 Vote Up0Vote Down
Hey all,

Making a small change in our forum management. Except for disruptive events related to religion, name-calling and insults (I don't have time to spell these things out and put them into an unacceptable category since we all need to use our own judgement at this stage about what's not acceptable) the Propeller 2 forum will have no moderation. This means threads won't be divided or locked, etc. We recognize that the design process has gone on for a very long time and that contributors are frustrated. Some have lament while others are joining the ARMy (the ongoing process is not funny but we best laugh a bit here and there). Your feelings are well-founded and since they're important to you they are of equal importance to us.

Chip has a very big responsibility towards the Parallax team, our customers, your customers, contributors, and the future of programming chips. This sort of forum management style may invite more friction, but at least the pressure relief valves are functional. Perhaps it'll help keep the contributors in a mode of contributing, too.

I don't think many microcontrollers have been designed in such an open environment. The open environment provides many big benefits: a design team; applications; advanced customers; a support system; and motivated people. Chip works alone and these benefits fit his style. At the same time it can also invite friction and discontent, affect sales of the current processor, and pose challenges internally at Parallax. Somewhere in here we have the job of trying to balance out the process and hold a tone.

Thanks,

Ken Gracey
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Comments

  • 44 Comments sorted by Date Added Votes
  • I asked Ken to make this change.

    Moderators, I appreciate your efforts and know that they are done with good intent. In this case, though, let's let things roll for a while and see how it goes.
  • Does that mean that the A "P2" - now or never - I'm off to join the ARMy thread will be unlocked?
  • Hadn't planned on it, but it sure could be unlocked. I don't have the power to do that, so I'll summon a moderator.

    Anybody have any power around here?
  • Hadn't planned on it, but it sure could be unlocked. I don't have the power to do that, so I'll summon a moderator.

    Anybody have any power around here?
  • ErNaErNa Posts: 976
    edited February 21 Vote Up0Vote Down
    I agree, it's not a good idea to close the discussion. We all are waiting for P2. For some time, things ran smoothly, really like a fine tuned machine, and then a discussion came up over features to enable higher level languages. What was Peters message? It is just a fact, we all have to earn money and we certainly can compete with those which earn money programming mainstream CPU's. But we know, the P1 is and P2 will be much better in many aspects. And now with the logic not yet frozen, TTS (Time to silicon) again will be prolonged. Peters Tachyon is a one man show and I'm unhappy, others and me do not support him with fill throttle. Hope to succeed soon. I believe, focus on C was not a big advantage for the propeller, BlocklyProp hopefully will do the job. Just complete P2 and the time will do the rest, with all the support of the powerful forum! And Tachyon will be a cornerstone to P2's success!

    addentum: I made realistic use of a sentence, that was shortly known for sarcasm. At least, I tried and mean it earnest!
  • potatoheadpotatohead Posts: 8,505
    edited February 22 Vote Up0Vote Down
    Ken Gracey wrote: »
    Hadn't planned on it, but it sure could be unlocked. I don't have the power to do that, so I'll summon a moderator.

    Anybody have any power around here?

    I have to chuckle: No Moderators. (Thanks for your service mods)

    First order of business is? Ummm, moderation?

    :D

    @all

    Its been rough. I've had my moments, though not recently. (REP labels anyone? Ugh)

    Three things:

    Chip, do not lose your mojo. We have something great here. I believe that all the way down.

    I think highly of and respect everyone here.

    I see developing SPIN and C as core to our efforts. What good is hardware missing a great data or program path? We will regret not doing the fix forever! Maybe all of us can exercise restraint, test for bugs and if there is a change, its a bug fix, or something meaningful to the language environments we all know matter.

    My .02 :D

    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: http://forums.parallax.com/showthread.php?123709-Commented-Graphics_Demo.spin<br>
  • I have been mostly lurking quietly since the failed P2hot run. While the openness is a good thing for getting a wide range of ideas to Chip, it's also a tremendous source of stress as there will always be too many of those ideas to put in the actual silicon. I remember people campaigning hard for their pet P2 features when I attended the UPEW in 2011. (OMG has it been that long?) Thing is, while there is a lot of good to community input, I think it is also true that the P1 is so elegant exactly because Chip was able to disappear into his mancave lab and spin up his personal vision without interruption and interference. At some point you have to stop taking suggestions and just decide what you're going to do and try to make it work. The one thing I would say, given Parallax's current direction, is that the P2 needs to support a hardware stack for efficient C code execution. Maybe not even bother with Spin at all. If C is to be a major language on P2, let's just make C the language of P2 and be done with it. The split between Spin and C has almost completely halted development of new objects for I/O protocols and peripherals which was very lively back in the day. Now if you have a cool idea for controlling $COOL_NEW_THING the first thing you have to ask is which language to develop it in, because whatever you choose you're losing half your potential users.

    P1 wasn't designed for C and is always going to be a bit poor at running it. But that doesn't mean P2 needs interrupts or $COOL_FEATURE that obviously benefits some particular application. (Particularly if we're getting 16 cogs, why the hell do we need interrupts? What we need is stack pointers if you want to run C.) One of the great things about the P1 cog feature set is that you really can't point at anything and say "well that's just in there for $APPLICATION." Yeah, maybe you don't need eight PLL's and eight video generators and eight counter-timer arrays, but dang you can do some great and unexpected stuff with four of them here and there that you couldn't do with just one. And of course Chip hadn't recently had the life changing mortality revealing coronary event when he designed P1. Having been through that myself I realize it colors your perspective a bit.

    I guess what I'm saying is that Chip designed a hell of a microcontroller in the P1, and I trust him to do it again even if I don't get all the ponies I want. There will always be something else that could have been put in P2 that would have made it better that isn't there. But at some point you have to decide what you're going to do, realize it's not going to be perfect because nothing in this world is, and just do it because the perfect is the enemy of the good.
  • How about giving away FPGA boards to anybody in the forum who wants to help test and verify the P2?
    This will speed up the verification process.
    There is no such thing as bad news.
  • localroger wrote: »
    ...The one thing I would say, given Parallax's current direction, is that the P2 needs to support a hardware stack for efficient C code execution. Maybe not even bother with Spin at all. If C is to be a major language on P2, let's just make C the language of P2 and be done with it. The split between Spin and C has almost completely halted development of new objects for I/O protocols and peripherals which was very lively back in the day. Now if you have a cool idea for controlling $COOL_NEW_THING the first thing you have to ask is which language to develop it in, because whatever you choose you're losing half your potential users.
    The VHDL and Verilog struggles in FPGA-Land, were largely solved by vendors supplying both languages.
    HLL issues in PC land can be helped by using things like DLLs, whence the source language does not matter.

    Someone has already suggested to make sure Spin-P2 be able to call C-P2, and vice-versa, and that would help the Library development you mention.
  • jmg wrote: »
    localroger wrote: »
    ...The one thing I would say, given Parallax's current direction, is that the P2 needs to support a hardware stack for efficient C code execution. Maybe not even bother with Spin at all. If C is to be a major language on P2, let's just make C the language of P2 and be done with it. The split between Spin and C has almost completely halted development of new objects for I/O protocols and peripherals which was very lively back in the day. Now if you have a cool idea for controlling $COOL_NEW_THING the first thing you have to ask is which language to develop it in, because whatever you choose you're losing half your potential users.
    The VHDL and Verilog struggles in FPGA-Land, were largely solved by vendors supplying both languages.
    HLL issues in PC land can be helped by using things like DLLs, whence the source language does not matter.

    Someone has already suggested to make sure Spin-P2 be able to call C-P2, and vice-versa, and that would help the Library development you mention.
    One way to make this happen would be to adopt spin2cpp aka fastspin as the official Spin compiler for the P2.

  • How about giving away FPGA boards to anybody in the forum who wants to help test and verify the P2?
    This will speed up the verification process.

    How do I put this tactfully?

    Amortizing the FPGA Propeller 1-2-3 Development Board non-recurring engineering (NRE) costs across the number of boards we produce they cost about $2,500 each even though the BOM costs of the board are around $400. We've done this a number of times already and it's a very expensive way to get results.
  • David Betz wrote: »
    jmg wrote: »
    Someone has already suggested to make sure Spin-P2 be able to call C-P2, and vice-versa, and that would help the Library development you mention.
    One way to make this happen would be to adopt spin2cpp aka fastspin as the official Spin compiler for the P2.

    Sounds worth exploring to me.
    Is there a table of the benefits of both approaches ?

  • If there needs to be C, then Spin/C/Spin interoperability would really be nice. That would help to heal the schism between the two languages and promote the art of P2 programming, regardless of which language a person chose to write in. If I wanted to develop a module in Spin, I could then rest assured that a C programmer could use it, and vice versa.

    -Phil
    “Perfection is achieved not when there is nothing more to add, but when there is nothing left to take away. -Antoine de Saint-Exupery

  • Kudo's to Chip for pressing for more relaxed moderation.

    I think it would help reduce angst, and quite possibly rekindle people's interest and an inclination to donate their time to help testing if we were able to get a State of the Prop2 from Chip.

    Review H/W requirements, done, not done, estimation on completion

    Same for S/W, instructions, C/Spin2 progress, est. on completion

    Formalize testing, what and how, prefferably with Who. Can we get a list of areas that are considered 'Done', not expected to change and thus able to be tested?

    We have 1 man basically, doing h/w and s/w.
    How many people do we have testing?

    Ken mentioned NRE of 2.5K per board with an MSRP of 400. Far as I know, Parallax has PnP machines doing the stuffing, so every board anew made should be coming out at lower and lower cost as there should be no more NRE expense, unless they are each hand-made ?

    No matter what, testing all the h/w and feature sets is going to take x amount of time.
    Every week, month or quarter that P2 is delayed due to a handful of testers is going to cost Parallax how much?
    I can't contribute anything useful testing-wise with or without a board. However I think others here are, and having another dozen testers out there working basically for free seems cost effective. Heck, even hiring 1 additional engineer solely to help get testing done at Rocklin would be far, far more expensive, even if they were nearly as qualified as many here.

    Cutting testing down to 1/2x or 1/3x should mean that much sooner you get to a shuttle date, potentially launch, and start revenue.





    ---- This space available for rent ----<br>
  • localroger wrote: »

    I think it is also true that the P1 is so elegant exactly because Chip was able to disappear into his mancave lab and spin up his personal vision without interruption and interference.


    While the openness is a good thing for getting a wide range of ideas to Chip, it's also a tremendous source of stress as there will always be too many of those ideas to put in the actual silicon.

    Maybe not even bother with Spin at all.



    Nobody want's Chip to disappear into a cave to complete work on the P2. And I can only imagine that diverting his thinking process can work both ways. Hope he can cancel out any stress involved, thoughts flow easier that way.

    But hasn't it been fun, that he has let you peek and poke into his mind. It is amazing to me that someone can do what he does on such a grand scale.

    I hope spin will continue on in some form, if not, that would be the end of the P1's popularity. The combination of the Propeller and Spin (Propeller Tool) is just plain fun.
  • koehler wrote: »
    Ken mentioned NRE of 2.5K per board with an MSRP of 400. Far as I know, Parallax has PnP machines doing the stuffing, so every board anew made should be coming out at lower and lower cost as there should be no more NRE expense, unless they are each hand-made ?

    No matter what, testing all the h/w and feature sets is going to take x amount of time.
    Every week, month or quarter that P2 is delayed due to a handful of testers is going to cost Parallax how much?
    I can't contribute anything useful testing-wise with or without a board. However I think others here are, and having another dozen testers out there working basically for free seems cost effective. Heck, even hiring 1 additional engineer solely to help get testing done at Rocklin would be far, far more expensive, even if they were nearly as qualified as many here.

    Cutting testing down to 1/2x or 1/3x should mean that much sooner you get to a shuttle date, potentially launch, and start revenue.

    I don't have a spreadsheet for this specific project so I have to talk about it generally (from experience I'm pretty sure I'm 90% accurate with the details, without researching numbers). Most of you could reverse-engineer these expenses as product developers.

    Yes, it's true that each additional Propeller FPGA 1-2-3 Development Board has a lower cost than the prior one because the NRE is spread across more boards [if we are selling the boards above our labor + materials costs]. It's quite common for engineers in a design process to think completion is near-term without consideration to their role in the whole entire project which would include the BOM, test procedure, documentation, communication with people around them, revisions, parts going obsolete during design, etc. If we put a schedule and timeline with true project management we often view things quite differently.

    The Propeller FPGA 1-2-3 Development Board likely has 600 hrs of design time in it. At a very low, blended, burdened rate (includes benefits, operating costs) that's at least $60,000 plus various fixed costs (software licensing, proto runs, subsystem tests, revisions) of another $10,000 and you're at $70,000. We even need to call on favors at neighboring manufacturing facilities for X-ray machines.

    At this stage I can almost hear all of our engineers saying "what, no way - you've got to be making this up!".

    This is what we do at Parallax, so we need to fit it in with all other efforts and make it work.

    I think we've built around 30 of these boards, scrapped a dozen and had 10 repaired by Tubular in Oz. BOM cost is around $300 each and we sell some, give some away, etc. In the end, we likely receive in revenue about $300 per board - there's really no hope or business reason in trying to recover any NRE.

    The NRE costs are part of the P2 R&D and this can't be viewed like a regular product. We receive tremendous benefit from the testers along the way - a team for Chip to do his work. I appreciate being able to handle these as an R&D expense far better than as a for-profit product.

    Bottom line is that these boards are a Propeller 2 R&D expense. They can be sold by Parallax or given away to key people for free - and while it helps to have a bit of revenue from them it's not going to make much of a difference in the scope of total R&D expenses (the fact most of you paid for them is tremendously appreciated). I have no objection to making more boards or giving them away for free provided we've got some clarity on our timeline, scope, and time to market. Without knowing (or estimating) these other pieces of the R&D puzzle the return on investment (ROI) can't be calculated or even guessed. I tend to like to remove or at least minimize the unknowns.

    To answer your question - Chip just has to request more boards and we'll build them. We can also give them away if he would like to do that. As a business manager I feel responsible to provide the details but also follow through on his request.

    Ken Gracey
  • Ken Gracey wrote: »
    To answer your question - Chip just has to request more boards and we'll build them. We can also give them away if he would like to do that. As a business manager I feel responsible to provide the details but also follow through on his request.

    To expand in this a little, Chip does release a number of FPGA image files, allowing P2 testing across a range of FPGA boards, some quite low cost.
    ie It is not mandated to have a Propeller FPGA 1-2-3 Development Board to test P2.

  • I'm on the brink of trying an FPGA image again. If things have stabilized and there is something for a DE0-Nano.
  • jmg wrote: »
    To expand in this a little, Chip does release a number of FPGA image files, allowing P2 testing across a range of FPGA boards, some quite low cost.
    ie It is not mandated to have a Propeller FPGA 1-2-3 Development Board to test P2.

    Yes this point needed to be corrected in the now closed thread. It isn't necessary to have latest FPGA hardware at all. Bemicro at $49 is cost effective if you can get it, but the DE0-Nano is my pick.

    The way to find proper bugs is through the applications like OzPropDev, GarryJ, Rjo, Rayman are developing. To my knowledge these are all being developed on Parallax FPGA (A7, A9) boards.

    I think images stabilized some time ago, Chip has been focused on fuses, documentation and software for some time now. There have been minor changes to verilog where required, but these are easy enough to track. The perception that things 'aren't stable' perhaps needs attending to.

    Heater, let us know if there is anything to help 'push you to the brink'

  • Tubular,

    A link to downloads, FPGA image and whatever software to drive it would do. Oh and some documentation.
  • Heater. wrote: »
    Tubular,

    A link to downloads, FPGA image and whatever software to drive it would do. Oh and some documentation.

    It's ALL in the first post of the "PROP2 FPGA FILES!!!" thread. You'll need Windows to run PNut.exe, though.
  • cgracey wrote: »
    Heater. wrote: »
    Tubular,

    A link to downloads, FPGA image and whatever software to drive it would do. Oh and some documentation.

    It's ALL in the first post of the "PROP2 FPGA FILES!!!" thread. You'll need Windows to run PNut.exe, though.
    Would it be possible to make that thread "sticky" so it stays at the top of the Propeller 2 forum? It's hard to find if it hasn't been updated recently.

  • BTW V15 of the FPGA images are available for P123-A7,P123-A9,DE0-Nano bare,DE0-Nano + add on,DE2-115+add pn,BeMicro Cv-A2 and BeMicro CV-A9.
    I'm lucky enough to have all of these and try to test code on them all where possible.
    Links to images and documentation is in the first post of the FPGA files thread.
    A complete list of instruction encoding is also included in the files for you compiler guys.
    :)
    Melbourne, Australia
  • Thanks Chip.
    You'll need Windows to run PNut.exe, though.
    I've still got that Surface Pro I hauled to Red Bluff last year. That should do it.




  • When I thought the P123 boards were all gone, I panicked a little as couldn't find anything nearly as good for sale anywhere...

    For some of my projects, I only need one P2, and since they are fairly well funded, would rather do it with P2V instead of fpga or P1...

    Anyway, just wanted to mention that I like the P123 board
    Prop Info and Apps: http://www.rayslogic.com/
  • :D
    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: http://forums.parallax.com/showthread.php?123709-Commented-Graphics_Demo.spin<br>
  • Rayman wrote: »
    When I thought the P123 boards were all gone, I panicked a little as couldn't find anything nearly as good for sale anywhere...

    Well, that's cool!
  • Rayman wrote: »
    When I thought the P123 boards were all gone, I panicked a little as couldn't find anything nearly as good for sale anywhere...

    For some of my projects, I only need one P2, and since they are fairly well funded, would rather do it with P2V instead of fpga or P1...

    Anyway, just wanted to mention that I like the P123 board

    Does that mean you can claim to have P2 system(s) deployed in the field ?
    Deserves some sort of plaque ? :)

  • jmgjmg Posts: 9,257
    edited February 23 Vote Up0Vote Down
    cgracey wrote: »
    It's ALL in the first post of the "PROP2 FPGA FILES!!!" thread. You'll need Windows to run PNut.exe, though.

    What level of x86 Assembler does PNut use ?

    I find this interesting link, that shows x86 is not as 'non portable' as some believe.....

    https://board.flatassembler.net/topic.php?p=184259#184259
    qemu-i386-static fasmarm
    

    above because fasmarm is coded in x86, using i386 level opcodes only.

    Screenshot:
    http://s17.postimg.org/9s1s9353j/Screenshot.png

    other info
    https://en.wikipedia.org/wiki/QEMU

    Has anyone used qemu ?

    Addit : there is also a video called
    3 Ways to Run x86 on Raspberry Pi
    on youtube, that covers other means too...

    and the commercial package (ExaGear) website is here...
  • [img][/img]
    Heater. wrote: »
    Thanks Chip.
    You'll need Windows to run PNut.exe, though.
    I've still got that Surface Pro I hauled to Red Bluff last year. That should do it.
    WAs that a year ago :(
    What have I done since then???
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
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