I am not a Verilog guy but I am a motivated fast learner
What I really want is a P1 with 2 clocks per instruction at 120MHz ie 60Mip Cores ( 3X speedup )
Ideally this would be an actual parallax ASIC but until then I am looking at the MAX10 as the target ( I saw P1V metrics at 133Mhz ).
Am I better to 'upgrade' the P1V Code to be 2 clocks per instruction ( Like the P2 )
Am I better to 'downgrade' the P2 Code to strip it back to a P1 to benefit from the 2 clocks per instruction already in the P2
The P2 Fpga release notes states
>* The Verilog source code is now capable of making any sub-version of Prop2
Does this mean I can already configure the P2 Verilog to conditionally compile out the 'non P1' logic to strip back to a P1 backward compatible core ( or close enough to it )?