Prop2 features not found on other offerings?

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  • Does any other micro-controller in the market have streamers?
    There is no such thing as bad news.
  • Mickster wrote: »
    Is the "P2 family" still being considered?

    Totally, yes. But it's hardly locked in stone. The previous examples Chip gave were just his first ideas - still much to happen before this bridge is truly crossed, and market demands will eventually shape things me thinks.
  • Does any other micro-controller in the market have streamers?

    I don't know ... they're fundamentally a DMA engine. Video displays are all of this ilk, albeit a fixed function DMA. Video out is exactly one of the intended uses of the Streamers but obviously they are more generic ... and there is one per Cog ... I wouldn't know what else comes close to that.
  • The P2 also has a Cordic solver, a very powerful feature. :)
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  • And the P2 empowers YOU in an unpresedented way
  • cgraceycgracey Posts: 8,009
    edited February 2 Vote Up0Vote Down
    Mickster wrote: »
    Is the "P2 family" still being considered?

    Yes. We'll make the big one first and then see how it goes.
  • Chip,
    Since you have the outer frame for the I/O now done in HL Software by Treehouse, I presume this can be shrunk/expanded to do various chip families?

    On this presumption, and the current P2 delays, might it be possible for the first P2 to be in a larger frame and have 1MB of Hub RAM?

    Still interested to know if OnSemi can put Flash/OTP/EEPROM in the chip and the cost factor?

    A P2 with 1MB HUB RAM and 1MB HUB FLASH/OTP/EEPROM able to be bank switched in say 64KB blocks could make for an extremely powerful and flexible P2, possibly in an QFP144 package. Extra pins would replace the ground pad underneath.
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
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  • Thanks for all the responses. This brings me up to speed.

    My next question is availability: When can we guestimate that we can have a physical P2 in hand?
    I did buy the FPGA equipment, but my brain and scheduled are not big enough to make progress with that.

    Are there any events scheduled (final design, test run, etc) that can give us an idea of where we are int he process and when we might expect something?

    +/- months or +/- years is what I'm hoping for in response.
  • P2 will be ready when it's done. No better estimate than that I am afraid.
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • evanhevanh Posts: 4,164
    edited February 6 Vote Up0Vote Down
    Cluso99 wrote: »
    On this presumption, and the current P2 delays, might it be possible for the first P2 to be in a larger frame and have 1MB of Hub RAM?
    The die is huge as is! You know that already. Please stop with the make it bigger requests.

    Still interested to know if OnSemi can put Flash/OTP/EEPROM in the chip and the cost factor?
    MRAM is superior in every respect, most of all it frees up a lot of die space without having to make the die bigger. However, all of these options require a more complex/expensive process, I believe, so none are on the drawing board.

    A P2 with 1MB HUB RAM and 1MB HUB FLASH/OTP/EEPROM able to be bank switched in say 64KB blocks could make for an extremely powerful and flexible P2, possibly in an QFP144 package. Extra pins would replace the ground pad underneath.
    Chip has chosen to use a ground pad for all variants to provide both the enhanced grounding for analogue I/O and also the needed heatsinking without needing an actual separate heatsink. You are asking Chip to forgo these advantages to make the die bigger and therefore more expensive and also use a more complex process and therefore even more expensive again.
  • jmgjmg Posts: 10,442
    edited February 6 Vote Up0Vote Down
    My next question is availability: When can we guestimate that we can have a physical P2 in hand?
    I did buy the FPGA equipment, but my brain and scheduled are not big enough to make progress with that.

    Are there any events scheduled (final design, test run, etc) that can give us an idea of where we are int he process and when we might expect something?

    +/- months or +/- years is what I'm hoping for in response.

    Depends what form 'a physical P2' takes.
    Right now, you can get a FPGA board, and work to 80MHz Digital.
    This is important for confirming the operation of the opcodes, and system design,

    eg see the posts around USB working on P2-FPGA & others around Display driving.

    USB capability is going to be quite important for P2.

    As well as USB connect, I'd like to see HyperRAM parts connected to P2-FPGA, so some idea of possible speeds can be derived, as well as confirming there is no simple oversight in the pin cells, that prevents useful HyperRAM operation.


    The P2 Code is in final bug-shakeout and tune stages, and Chip has done the PLL tuning.
    It could be passed to FAB immediately, but with higher risk of needing a respin.

    Once testing is deemed thorough enough to pass to FAB, there is a process delay to get shuttle samples, and then (much) more testing is needed, to generate an errata sheet for those samples.

    Parallax then need to decide if they can release parts with that errata, or if another pass is needed.

    Add all those delays up, and you have your full production release & shelf stock lead-time ;)
  • Just thinking...

    If the big P2 works right off and Chip makes the baby P2s:

    Perhaps a tiny P2 can be put in the big P2 package with other chips?
    Say a flash die? wonder if that would work...
    Prop Info and Apps: http://www.rayslogic.com/
  • Rayman wrote: »
    Just thinking...

    If the big P2 works right off and Chip makes the baby P2s:

    Perhaps a tiny P2 can be put in the big P2 package with other chips?
    Say a flash die? wonder if that would work...

    BGA tends to be the multi-die preference, as that allows flexible bonding.

    What may be possible with P2, is allowing for a stacked die flash.

    Some FPGAs do this, and I understand they literally stack a small flash die in one corner of the main FPGA die, then die-die bond to some internal pads.
    One detail then becomes, are those standard IO, or buried IO ?

    Certainly worth asking OnSemi about allowing for that, at the final design stages ?

  • evanhevanh Posts: 4,164
    edited February 7 Vote Up0Vote Down
    I'd hate to imagine the square mm's 1000 package bonds consume. It's probably not as bad as I'm thinking in terms of percentage as those type dies are well beyond huge in size, hence the $200 price tags.
  • evanh wrote: »
    I'd hate to imagine the square mm's 1000 package bonds consume. It's probably not as bad as I'm thinking in terms of percentage as those type dies are well beyond huge in size, hence the $200 price tags.

    If you are talking about the really big FPGAs with hundreds of IO, yes, I understand they have long since moved away from pad-rings, and now the IO pads are all over the die, and flip-chip packaging onto BGA is what they do.
    This is why they are only sourced as BGA.


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