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ozpropdev
Posts: **2,560**

in Propeller 2

Hi All

Can someone confirm the operation of the SCL/SCLU instruction.

It's my understanding the SCLU is basically a MUL instruction followed by a SAR 16 bits.

I assume the same goes for SCL, a MULS followed by a SAR 16 bits.

Is that correct?

If so, here is what I am seeing.

SCL seems to give a result tat is out by 2 bits.

* Test1 SCLU with unsigned values = Ok.

* Test2 SCL with unsigned values = Needs extra SAR 2 to be correct.

* Test3 SCLU with 1 signed value = Fails as expected.

* Test4 SCL with 1 signed value = Needs extra SAR 2 to be correct.

Can someone confirm the operation of the SCL/SCLU instruction.

It's my understanding the SCLU is basically a MUL instruction followed by a SAR 16 bits.

I assume the same goes for SCL, a MULS followed by a SAR 16 bits.

Is that correct?

If so, here is what I am seeing.

SCL seems to give a result tat is out by 2 bits.

* Test1 SCLU with unsigned values = Ok.

* Test2 SCL with unsigned values = Needs extra SAR 2 to be correct.

* Test3 SCLU with 1 signed value = Fails as expected.

* Test4 SCL with 1 signed value = Needs extra SAR 2 to be correct.

Test #1 R0 = $000004D2 0000001234 R1 = $000004D2 0000001234 MUL R0,R1 = $00173C44 0001522756 SAR 16 = $00000017 0000000023 SCLU R0,R1 = $00000017 0000000023 * SAR 2 = $00000005 0000000005 ========================================== Test #2 R0 = $000004D2 0000001234 R1 = $000004D2 0000001234 MULS R0,R1 = $00173C44 0001522756 SAR 16 = $00000017 0000000023 SCL R0,R1 = $0000005C 0000000092 * SAR 2 = $00000017 0000000023 ========================================== Test #3 R0 = $FFFFFB2E -0000001234 R1 = $000004D2 0000001234 MUL R0,R1 = $04BAC3BC 0079348668 SAR 16 = $000004BA 0000001210 SCLU R0,R1 = $000004BA 0000001210 * SAR 2 = $0000012E 0000000302 ========================================== Test #4 R0 = $FFFFFB2E -0000001234 R1 = $000004D2 0000001234 MULS R0,R1 = $FFE8C3BC -0001522756 SAR 16 = $FFFFFFE8 -0000000024 SCL R0,R1 = $FFFFFFA3 -0000000093 * SAR 2 = $FFFFFFE8 -0000000024

## Comments

11,693SCLU multiplies D[15:0] by S[15:0] and substitutes product >> 16 into the next instruction's S value. For example:

SCLU A,B 'Add (A[15:0] * B[15:0]) >> 16 into C

ADD C,0

SCL multiplies D[15:0] by S[15:0] and substitutes product ~> 14 into the next instruction's S value (~> is like SAR). For example:

SCL A,B 'Add (A[15:0] * B[15:0]) ~> 14 into C

ADD C,0

2,211This allows fractional multiply with one factor as a signed 16bit signal and the other factor as a coefficient in the range -2.0 .. +1.99994.

So the SAR by 2 you do in the Tests, is normally done by the correct scaling of the coefficient. $4000 correspond to 1.0.

Fractional multiply is important for DSP application where you work mostly in the range -1.0 to +1.0, Chip wanted to have the scaling so that 1.0 is possible. And for FIR filters the coefficients can go bigger than 1.0, so +-2 is a good decision.

The downside is that the resolution of the fractional part is only 14 bits now. For more resolution we would need a better multiplier with 18x18 bits or more.

Andy

2,560Melbourne, Australia7,841By doing that, we can more accurately measure their mass, and determine whether

scientists have systematically been underestimating how much matter they contain."