- Announcement about May 10th, 2018 update and your password.
Thought this should have its own thread.
I am not quite sure where to start.
These are some things I think will help with the testing...
1. Some form of data logging (logic analyser style)
Need to sample the USB bus (2 bits) at 12MHz = 83.3ns which is 4 clocks at 96MHz.
While oversampling is ideal, this should get us somewhere in the meantime.
How to achieve this ???
(a) Use a P1 (rather difficult to record a long length of data)
My RamBlade might be able to do this by storing the sample bits straight into the SRAM which would give 512K samples.
Perhaps use Peter's Splat (modified) to then display the samples.
(b) Use an FPGA board
Use a modified P1V to store the data. Could make instructions to aid the storage. Limited to cog/hub memory.
Use P2 code (2x faster) to store data into cog/hub.
Either could use an external 512KB SRAM (I have a suitable board - my MemBlade)
(c) Use an FPGA board and P2 smart pins to read the data and store the "bytes" as they are read in.
2. PC with USB Analyser software
I seem to recall that there is some software that can be used to monitor the USB Driver. Need more research.
Any other ideas??? Or comments on the above???