The concept behind the P1, and initially the P2, was that some of the cogs would be dedicated to handling the I/O Pins.
After the P2-HOT came 16 cogs and more hub ram, but lower spec cogs.
Somewhere along the way came some ideas about putting some smarts into the I/O pins themselves. This has grown to a large LUT/ALE space for all sorts of things, including placing the counters there too. This means that we also need some primitive counters in the cogs as well.
I wonder what could be achieved with a number (say 8?) of tiny cpu's specialised for handing a group of I/O pins?
For fun (I have seen the other thread about naming the smart pins), lets call these "tappets" (part of an engine) for now.
What would these "tappets" (cpu's) require?
The cpu could be 8 bits with a small sram memory and say 16 internal addressable registers.
The cpu could access a group of 8 I/Os selected from 64. Multiple cpu's could operate in parallel like cogs (OR outputs).
A few simple instructions like AND/OR/XOR/ANDN and SHIFT IN/OUT PIN instructions to accumulate the bits easy.
Perhaps it could clock faster than the cogs because of the smaller and simpler instruction set.