Prop2 FPGA files!!! - Updated 2 June 2018 - Final Version 32i

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  • Many companies are making 1117 regulators. They are my current favorite...
    Prop Info and Apps: http://www.rayslogic.com/
  • jmgjmg Posts: 12,325
    Rayman wrote: »
    Many companies are making 1117 regulators. They are my current favorite...

    Yes, the series should be available 'for ever', and the older ones have Iq of < 6~10mA and dropouts of < 1.4V @ 0.8A.
    Being generic keeps the price down too.... LDL1117 show as low as 10c/3k from Future, and cheapest xxx117 are as low as 3.7c/1k from asia..
  • cgraceycgracey Posts: 9,984
    edited June 21 Vote Up0Vote Down
    The power test was done at 180MHz. The pin toggle rate was clock/8. This was only 1.8V core power, not 3.3V I/O power. Not sure what the I/O power will be, but it will be a heck of a lot less than the core.

    The leakage test was done at whatever corner would produce the most leakage. I believe this was at fast process, high voltage, and high temperature. I think we will probably see 50ua.
  • Do I recall correctly, or did I read previously read the static leakage was going to be 1 mA or something?

    The reason I ask is because 50 uA significantly opens up possible applications

    I am the Master, and technology my slave.
  • The_Master wrote: »
    Do I recall correctly, or did I read previously read the static leakage was going to be 1 mA or something?

    The reason I ask is because 50 uA significantly opens up possible applications

    That's right. My early assumption was 1ma of leakage.
  • I just took a look at the Prop1 datasheet. It says quiescent current under special conditions can be as low as 600 nA. That seems really low for such a complex IC. Nice.

    What surprised me more though is the max power rating of 1 Watt. Surely the Prop1 can't get near that figure. I'm wondering if maybe that 1 W also includes load devices on the I/O pins?

    "Are we alone in the universe?"
    "Yes," said the Oracle.
    "So there's no other life out there?"
    "There is. They're alone too."
  • Peter JakackiPeter Jakacki Posts: 7,809
    edited June 21 Vote Up0Vote Down
    Isn't the 1W figure the absolute power "handling" capability of the package? For instance if we pushed all 8 cogs so that it consumed 330mW max @100MHZ @25'C then we shouldn't push more than 670mW "dissipation" through the I/O etc. Not really the kind of figures we're after though.

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  • TubularTubular Posts: 3,221
    edited June 21 Vote Up0Vote Down
    evanh wrote: »
    I just took a look at the Prop1 datasheet. It says quiescent current under special conditions can be as low as 600 nA. That seems really low for such a complex IC. Nice.

    What surprised me more though is the max power rating of 1 Watt. Surely the Prop1 can't get near that figure. I'm wondering if maybe that 1 W also includes load devices on the I/O pins?

    1 watt isn't huge. Think of it as four 1/4 watt through hole resistors running at rated power and covering a similar circuit board area.

    The load devices dissipate their own energy but remember they are switched by transistors with a ~28 ohm Ron resistance, at 25mA those dissipate 17.5mW per pin, while powering an external load which might be dissipating ~65mW. So that 17.5mW times 30 pins is 0.525 watts, in addition to what the core consumes.

    This is an unlikely application - in practice those pins would probably have some kind of duty cycle, and plus there's about a 400mA current in the datasheet limit I believe, but it shows how things can add up.

  • RaymanRayman Posts: 8,832
    edited October 2 Vote Up0Vote Down
    ozpropdev wrote: »
    New P123-A7 image is Ok Chip.
    I did have to put a pullup on P59 to get a bare board to respond.
    That might have been the problem with the previous version.
    I'll check...

    Guess we should have looked into this more...

    Prop Info and Apps: http://www.rayslogic.com/
  • evanh wrote: »
    I just took a look at the Prop1 datasheet. It says quiescent current under special conditions can be as low as 600 nA. That seems really low for such a complex IC. Nice.

    What surprised me more though is the max power rating of 1 Watt. Surely the Prop1 can't get near that figure. I'm wondering if maybe that 1 W also includes load devices on the I/O pins?
    Ah, of course, the wattages mentioned for the Prop2 so far are only for the 1.8 V core rail. The 3.3 V I/O rail will have additional power losses. Where as that 1 W is an all-in-one figure for the Prop1.

    "Are we alone in the universe?"
    "Yes," said the Oracle.
    "So there's no other life out there?"
    "There is. They're alone too."
  • cgracey wrote: »
    My early assumption was 1ma of leakage.
    That's a number to remember. I seem to be forgetting much of what I've read.

    "Are we alone in the universe?"
    "Yes," said the Oracle.
    "So there's no other life out there?"
    "There is. They're alone too."
  • jmgjmg Posts: 12,325
    evanh wrote: »
    cgracey wrote: »
    My early assumption was 1ma of leakage.
    That's a number to remember. I seem to be forgetting much of what I've read.

    A measurement is even better, than an 'early assumption' ... :)
    I've not seen a static Icc number yet, but my Cpd modeling suggested intercept of ~5mA, from Chip's measurements so far....
    (maybe that includes a Crystal, not sure what connections Chip is using ? ( MHz Xtal / Osc ? )
  • RaymanRayman Posts: 8,832
    edited October 10 Vote Up0Vote Down
    How do you access the ADC?

    I just searched through the docs and don't see any details...

    I'm curious to see how fast we can get 8 bit samples...
    Prop Info and Apps: http://www.rayslogic.com/
  • cgraceycgracey Posts: 9,984
    edited October 10 Vote Up0Vote Down
    Rayman wrote: »
    How do you access the ADC?

    I just searched through the docs and don't see any details...

    I'm curious to see how fast we can get 8 bit samples...

    When you put a pin into ADC mode, it begins returning a stream of bit samples on the IN pin, which must be summed up to get a conversion. There are smart pin modes which tally up these bits over time. I will put up an example in a little bit.
  • RaymanRayman Posts: 8,832
    edited October 10 Vote Up0Vote Down
    Ok thanks. Sounds like 256 clocks for 8 bit then...

    Guess 1 MHz acquisition at 256 MHz clock then ...
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  • Rayman wrote: »
    Ok thanks. Sounds like 256 clocks for 8 bit then...

    Guess 1 MHz acquisition at 256 MHz clock then ...

    The P2 needs testing of multiple analog channels to get ENOB vs Sysclk, but with P2’S higher rfb and fixed Cn, I doubt you will get 1Msps / 8b ENOB
  • RaymanRayman Posts: 8,832
    edited October 10 Vote Up0Vote Down
    ENOB seems always less than # bits you get... Hopefully will be >7.0
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  • Rayman wrote: »
    ENOB seems always less than # bits you get... Hopefully will be >7.0

    True,but P2 uses Vcc,gnd as reference, so best analog will likely need 4 Layers and back-side decoupling, along with ferrite beads, & including SMPS will need extreme care, as there is no analog gnd pin.
  • I imagine you'd want to use an external buffer amp for best results...
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  • On the test board that we did, which plugged onto the Prop-123 FPGA board and used its 3.3V supply, I was getting 11.5 bits of steady reading, with the lower bits looking noisy. That was on a very noisy platform. I am anxious to see what kind of stability we will get when we use a clean power supply.

    If you run at 256MHz, you will get 8-bit ADC conversions at a 1MHz rate.
  • cgracey wrote: »
    On the test board that we did, which plugged onto the Prop-123 FPGA board and used its 3.3V supply, I was getting 11.5 bits of steady reading, with the lower bits looking noisy. That was on a very noisy platform. I am anxious to see what kind of stability we will get when we use a clean power supply..
    .. and fitting all the decoupling caps ! ;)

    Can you vary the SDM FF clock speed, or is that set at always SysCLK ?

  • Rayman wrote: »
    I imagine you'd want to use an external buffer amp for best results...

    Yes, always a good idea and reduces cross-talk on the way into the pin.
    Best Buffering is trickier on P2, as the reference differential, is a CMOS gate threshold. Thus PSRR is lousy.

    Ideally, the external buffer should use that same reference point, but I don't think that can come to a pin, or drive into a pin ?

    Hmm.. If an ADC is run with a large CAP right at the pin, does that give a HiZ Vref (well, at least of an adjacent channel)

    Using that, could reduce temperature drift effects & improve PSRR ? - external buffer is then a dual opamp.
  • jmg wrote: »
    cgracey wrote: »
    On the test board that we did, which plugged onto the Prop-123 FPGA board and used its 3.3V supply, I was getting 11.5 bits of steady reading, with the lower bits looking noisy. That was on a very noisy platform. I am anxious to see what kind of stability we will get when we use a clean power supply..
    .. and fitting all the decoupling caps ! ;)

    Can you vary the SDM FF clock speed, or is that set at always SysCLK ?

    The ADC always operates at the system clock.
  • Rayman wrote: »
    I imagine you'd want to use an external buffer amp for best results...

    Maybe for higher bit counts, I doubt it will matter if aiming for 8~10 bit resolution.

    I think Chip has indicated ADC input impedance is around 500 kohms, which will do fine for most applications. That impedance figure is a lot higher than many ADCs.

  • jmg wrote: »
    Rayman wrote: »
    I imagine you'd want to use an external buffer amp for best results...

    Yes, always a good idea and reduces cross-talk on the way into the pin.

    Ideally that buffer needs to be at the sensor, not near the P2, so you drive the entire input line at a low impedance
    Best Buffering is trickier on P2, as the reference differential, is a CMOS gate threshold. Thus PSRR is lousy.

    Well the power supply isn't the digital core supply, its the local supply to that ADC pin an 3 neighbors. So you could use a proper reference IC for this, they're often good for a few mA, assuming you're not doing some crazy digital switching on those neighbors.

    There are also some really good low noise linear regulators for this kind of thing.
    Ideally, the external buffer should use that same reference point, but I don't think that can come to a pin, or drive into a pin ?

    If you wanted, you could expose that reference potential from its neighbor. There's a feedback mode on P1 counters that hunts that 1.4~1.6v threshold I think you're talking about. That might need to be from the adjacent unloaded pin
  • Tubular wrote: »
    Best Buffering is trickier on P2, as the reference differential, is a CMOS gate threshold. Thus PSRR is lousy.

    Well the power supply isn't the digital core supply, its the local supply to that ADC pin an 3 neighbors. So you could use a proper reference IC for this, they're often good for a few mA, assuming you're not doing some crazy digital switching on those neighbors.

    There are also some really good low noise linear regulators for this kind of thing.
    -- it's not just Vio that needs to be clean, any ground noise, or ground movement, is going to 50% impose on the Analog reference too, via that CMOS gate threshold effect.
    There is no separate Analog Gnd, so even a few millivolts movement in GND will cause crosstalk.
    10 bits at 3v3 needs < 3.3mV movements.


  • Can I run an FPGA board at 40 MHz instead of 80 MHz? From the docs it looks like I could us "HUBSET #$0F" instead of "HUBSET #$FF" to divide the system clock by 2, but this doesn't seem to work. What is the correct setting for HUBSET to get 40 MHz?
  • My memory is we only had 80, and possible 20 MHz
  • -- it's not just Vio that needs to be clean, any ground noise, or ground movement, is going to 50% impose on the Analog reference too, via that CMOS gate threshold effect.
    There is no separate Analog Gnd, so even a few millivolts movement in GND will cause crosstalk.
    10 bits at 3v3 needs < 3.3mV movements.

    Jmg lets move this subthread over to the silicon observations thread as its really nothing to do with the FPGA images, that some people are firing up with renewed interest now P2 silicon exists.
  • Dave Hein wrote: »
    Can I run an FPGA board at 40 MHz instead of 80 MHz? From the docs it looks like I could us "HUBSET #$0F" instead of "HUBSET #$FF" to divide the system clock by 2, but this doesn't seem to work. What is the correct setting for HUBSET to get 40 MHz?

    Dave, this should work:

    HUBSET #$7F '40MHz

    Bits 7..4 select 5MHz..80MHz in 5MHz increments.
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