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Prop2 FPGA files!!! - Updated 2 June 2018 - Final Version 32i - Page 148 — Parallax Forums

Prop2 FPGA files!!! - Updated 2 June 2018 - Final Version 32i

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  • evanhevanh Posts: 15,091
    Okay, I'll eat my words on that point. It would appear I wasn't careful enough on the reader comparison. I'm getting an easy sustained 65+ MB/s using the other good reader.

    Thanks for the nudge. Saves me making a fool of myself tomorrow!

    I'm guessing there is a power problem. I do have trouble getting cards to even register sometimes. The third reader I mentioned only detects some SD cards. It's fine for CF cards, they have a sturdy connector.

    Here's the graphs using the second card reader. Left most blob is the Kingston SD card writing six files totalling almost 12 GB. Middle blob is the Sandisk SD card writing the same six files. And finally the second piccy has the 10 GB block write to the Sandisk card.
  • Does the reader have a usb cable?

    I've been burned by USB devices coming with cables that can't sustain the power draw even of the device they were sold with.
  • evanhevanh Posts: 15,091
    Yeah, looks like the USB controllers/bridges are partly to blame here. After a power cycle of the whole PC, things are more alive. It's no faster but I've got that third card reader, the 5.25" bay, back in action and more all round seems to work. So there was some bugginess along the device chain getting in the way before. I'm slightly suspicious of the first card reader, the Kingston, on top of the PC, reader being the cause. See photo below.

    The USB cables are quite chunky. I feel they're okay. The 5.25" bay power is from a 5.25" FDD/HDD power plug.

    It's becoming notable that some readers are marked as USB3 SuperSpeed but cap out at a flat 40 MB/s. Which is better than what USB2 devices ever achieved in practice but that's before it got a performance bump late in the piece. This applies to the Silverstone 5.25" bay card reader and also the Mbeat reader - another card reader I just found.

    The only card reader that provides full speed sustained is the small Transend reader in the left most USB socket of the bay.
    842 x 1224 - 143K
  • Peter JakackiPeter Jakacki Posts: 10,193
    edited 2018-06-01 15:33
    evanh wrote: »
    The only card reader that provides full speed sustained is the small Transend reader in the left most USB socket of the bay.

    I use one of those ones too that came with the Transcend WiFi card plus the card plugs in at right angles and it also takes microSD. I must try out the WiFi card in a unit.

    EDIT: Looks like those WiFi cards don't support SPI mode. I try to issue a 0 0 CMD to it in TAQOZ but it keeps coming back with $80 instead of $01.

  • Cluso99Cluso99 Posts: 18,066
    Peter,
    Did you answer what the old SD card responded to CMD8 with?
    FWIW If it was $05 then that is a legitimate reply - Illegal command, and I cater for it.
  • Yes, you can see in the docs that it was a 05 which is a valid negative response
  • Cluso99Cluso99 Posts: 18,066
    Yes, you can see in the docs that it was a 05 which is a valid negative response

    Which I believe my code correctly handles as an SD type 1. It does not terminate as it's just an old card and I handle those fine as long as they are FAT32 formatted.
  • Cluso99 wrote: »
    evanh wrote: »
    “What car did you learn to drive stick shift on?” == “What was the make and model of your first car?” -> Password reset!

    What's a stick shift???
    I learn't on a column shift! Right hand shift, right hand drive in Oz.
    Actually, I lied. I learnt on a VW floor shift, then the '52 IH truck.

    Gotta love those corn binders.
  • evanh wrote: »
    Yeah, looks like the USB controllers/bridges are partly to blame here...

    Hi evanh

    I'm seeing that you're using the front-panel accessible USB ports of your pc.

    Despite the convenient reaching of front-panel accessible USB connectors, at least in my home pc setup, there is some evidence of bad transfer rates, just at those connectors, e.g., when I use a external hd (USB-2 and USB-3). Also, sometimes, either external hd fails to be properly recognized, when connected to any of the front-panel USB ports.

    Most of the times, changing the USB port where the drive was initialy connected, at the front-panel, is enough to resolve the recognization issue, though that procedure does not solve the poor transfer rate issues, never.

    By attaching the external drives (I have two, so I was able to test them, independently) to any of the rear-panel accessible USB ports (at my systerm, the ones that are directly soldered to the motherboard, without intervening cables or connectors, inside the hood) they ever displayed better sustained transfer rates and never fail to be recognized, at first try.

    Sure, I know that external HDs would consume a lot more power than any USB-enabled SD card reader, an that fact could explain the difficulty of recognizing it, but, perhaps, it helps trying your system's back-panel USB ports, at least to check for any difference in the transfer rates, as I have noticed on my system's operation.

    Henrique

  • evanhevanh Posts: 15,091
    edited 2018-06-02 10:32
    Henrique,
    Ah, these ones are a little different to what you have. Note it fills a 5.25" bay. There is a 5.25" power plug powering that bay unit. Inside, the two USB3 ports of the internal plug from the motherboard will be used independently:
    - One will be just for the low grade card reader slots. Would have been nice if these were faster.
    - The other will be feeding a USB3 hub controller chip which splits out to the three blue USB sockets. The fourth red socket is just a charging port.

    So, strong power and USB controller is direct PCB to those blue USB sockets.

    The two blue USB sockets in the case above the DVD drive are not plugged in internally. Mainly because the motherboard only has one USB3 internal socket. If they had a USB2 internal plug then I would have used them.

  • Hi evanh

    Many thanks by having it explained to me. Truly different from the ones under my possession.

    As I only had the photo you've posted as an input, I'd almost immediately tryed to relate it to my younger system (the better one, if it can be called in such way; Prince Retard, The Sequel). I also have another one, a trully ancient (fourteen y. o.) Asus/Amd; (King Retard, The First).

    The simple fact they are yet able to power-on and boot is a daily surprise, as a double yolk egg, extra bacon, for the breakfast. :smile:

    Good to know you have a better one.

    Henrique
  • cgraceycgracey Posts: 14,131
    I posted a new v32i at the top of the thread. Same name "v32i" as before, but with a hopefully-fixed Prop123-A7 file.

    Here it is:

    https://drive.google.com/file/d/1huxRvHmr07ItoO06rLYGsOKmMQVEOA4R/view?usp=sharing
  • cgracey wrote: »
    I posted a new v32i at the top of the thread. Same name "v32i" as before, but with a hopefully-fixed Prop123-A7 file.

    Here it is:

    https://drive.google.com/file/d/1huxRvHmr07ItoO06rLYGsOKmMQVEOA4R/view?usp=sharing
    New P123-A7 image is Ok Chip.
    I did have to put a pullup on P59 to get a bare board to respond.
    That might have been the problem with the previous version.
    I'll check...

  • Sorry Chip, looks like previous A7 version was Ok too. :blush:
  • Maybe the A7 board behaviour is different because of the 2.5V I/O on P32-63?
    Anyhow it's all good now.
  • Hmm interesting

    Might be worth seeing what lsio in Tacoz reports, when nothing is connected
  • Tubular wrote: »
    Hmm interesting

    Might be worth seeing what lsio in Tacoz reports, when nothing is connected
    Here's the lsio result with pullup and without pullup.
      Cold start
    ----------------------------------------------------------------
      Parallax P2  .:.:--TAQOZ--:.:.  V1.0--142          180530-0135
    ----------------------------------------------------------------
    TAQOZ# lsio
    P:00000000001111111111222222222233333333334444444444555555555566
    P:01234567890123456789012345678901234567890123456789012345678901
    =:dd~~d~~~~~~~~~~~~~~~~~d~~~~~~d~d~~~~~~~~~~~~~~~~~d~~~~~hhh~h~~ ok
    TAQOZ# lsio
    P:00000000001111111111222222222233333333334444444444555555555566
    P:01234567890123456789012345678901234567890123456789012345678901
    =:dd~~d~~~~~~~~~~~~~~~d~d~~~~~~d~d~~~~~~~~~~~~~~~~~d~~~~~hhh~d~~ ok
    TAQOZ#
    


  • Peter JakackiPeter Jakacki Posts: 10,193
    edited 2018-06-03 09:49
    ozpropdev wrote: »
    Here's the lsio result with pullup and without pullup.

    So it looks like that when it has a pullup that it prioritizes serial but without then there is an internal pulldown so it disables serial.

  • Any update on what's happening with the P2 chip progress?
  • I haven't noticed Chip online for several days now and he hasn't come back with any reports which probably means he's still buried in sims with On Semi and they haven't proceeded to tapeout yet. I hope it's not like the P2HOT scenario though although I doubt it since the full FPGA version runs from a USB port and dedicated silicon will fare far better. However it is probably wise not to jump to or discuss possible conclusions, just wait as I'm sure we will hear back this week.

  • cgraceycgracey Posts: 14,131
    edited 2018-06-20 23:45
    I've kind of been on summer vacation while On Semi finishes up the simulations.

    As of today, we checked the waveforms from the final simulations and everything looks perfect.

    They're going to have some paperwork for me to sign on Friday and tape-in in will proceed on Monday. After DRC checks on the mask data, tape-out will happen and we will be on the way to getting chips built. I think it will take 15 weeks before we see chips.

    We did some worst-case power checks. These were under fastest process conditions, highest voltage, and lowest temperature. The results are probably 50% in excess of what anybody will ever see. I wrote a program which enabled all smart pins in PWM mode, all cogs, and all hub FIFO's. Also, each cog issues a CORDIC command every 16 clocks. The power came in at 2.05 Watts. Leakage was only 134ua. These numbers are way better than what the tool was estimating, based on 20% toggling.

    So, it's time to think about tools.
  • TubularTubular Posts: 4,620
    edited 2018-06-20 23:55
    Brilliant news, Chip. Congratulations on your efforts.

    Leakage is lower than expected, we can easily battery back that for security, and that xcl220 regulator jmg found to looks possible

    I'd just like to point out (OzPropDev is my witness) that I nominated "2 watts", though thought it was a chance of going considerably higher with all the packed in extras.


  • I had my head set on 2W max max so that figure sounds good. But do you have any details on 1.8V vs 3.3V power?
  • All the numbers are looing good Chip!
    Excellent mews. :)
  • Cluso99Cluso99 Posts: 18,066
    Fantastic news :):):)
  • Cluso99Cluso99 Posts: 18,066
    Chip,
    Does the 15 weeks include packaging the first dice or is that additional?
    15 weeks would be around mid-October.
  • RaymanRayman Posts: 13,767
    edited 2018-06-21 00:43
    This sounds great. P1 is 0.1 A at 100 MHz with all cogs running spin loops (from datasheet) at 3.3 V and 25 C. I think that is 0.33 W.

    P2 is 8X faster maybe? Guess that would make 2 W look good...
  • cgracey wrote: »
    I've kind of been on summer vacation while On Semi finishes up the simulations.

    As of today, we checked the waveforms from the final simulations and everything looks perfect.

    They're going to have some paperwork for me to sign on Friday and tape-in in will proceed on Monday. After DRC checks on the mask data, tape-out will happen and we will be on the way to getting chips built. I think it will take 15 weeks before we see chips.

    We did some worst-case power checks. These were under fastest process conditions, highest voltage, and lowest temperature. The results are probably 50% in excess of what anybody will ever see. I wrote a program which enabled all smart pins in PWM mode, all cogs, and all hub FIFO's. Also, each cog issues a CORDIC command every 16 clocks. The power came in at 2.05 Watts. Leakage was only 134ua. These numbers are way better than what the tool was estimating, based on 20% toggling.

    So, it's time to think about tools.
    Thanks for the update. It's lookin' good!

  • jmgjmg Posts: 15,140
    edited 2018-06-21 01:16
    cgracey wrote: »
    We did some worst-case power checks. These were under fastest process conditions, highest voltage, and lowest temperature. The results are probably 50% in excess of what anybody will ever see. I wrote a program which enabled all smart pins in PWM mode, all cogs, and all hub FIFO's. Also, each cog issues a CORDIC command every 16 clocks. The power came in at 2.05 Watts. Leakage was only 134ua. These numbers are way better than what the tool was estimating, based on 20% toggling.
    Great news - do you have exact applied voltages, and MHz used for this test, and the mA from each rail ?
    What was the 3v3 Pin toggle rate in this test ? is that 62 ? 60 ? pins in PWM ? ( 60! PWMs is certainly going to get people's attention !)

    'Lowest temp' is not going to stay lowest for very long at 2W ;) - how much does Icc vary with temperature ?

    Was that 134uA leakage the worst case value, or the one at lowest temp ?
  • jmgjmg Posts: 15,140
    Tubular wrote: »
    Brilliant news, Chip. Congratulations on your efforts.

    Leakage is lower than expected, we can easily battery back that for security, and that xcl220 regulator jmg found to looks possible
    Yes, very good news.

    Those numbers also mean the 1A+ Linear regulators can be looked at, knowing they will handle the peak numbers. It's then up to users to mostly sleep, to keep average thermal envelope still ok for linear regulators.'
    This makes the ST LDL1117 I've suggested a particularly good fit for linear regulator choices, not pushing the envelope. Series diodes can be added to spread the power footprint. eg SMB 2A are low cost
    SMPS would be used for very top end, or someone wanting to stay inside the 500mA USB limit.

    LDL1117
    1.2 A Max, dropout voltage of Typ 350 mV Max 600mV @1.2A PSRR 87 dB at 120 Hz, Iq Typ 250μA
    Load regulation (IOUT = 10 mA to 1.2 A -40 °C < TJ < 125 °C) Typ 5mV
    θJ-C Thermal resistance junction-to-case 15 °C/W SOT223
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