Dark Silicon

cgracey

David Betz sent me some things to read about the RISK V project that were interesting. Linking from those resources, I started reading about what has been termed "Dark Silicon", which is an outcome of processes shrinking faster than energy-per-function, so you can practically only clock a portion of your silicon at full speed, due to heat buildup or shear power constraints. In 8 years' time, only 1/16 the area of a leading-edge chip will be able to clock at full speed. This leads to interesting future design considerations. Here is a paper about it:

http://darksilicon.org/papers/papers/taylor_dark_silicon_horsemen_dac_2012.pdf

potatohead

I found this one very illuminating on the core dynamics and options available: http://cseweb.ucsd.edu/~mbtaylor/papers/taylor_landscape_ds_ieee_micro_2013.pdf

It's linked from the one you put here Chip. Tons of other good stuff there, but this is one I'm reading with great interest! Explains a whole lot.

evanh

That's mostly talking about logic area I suspect, as far as I can tell they are talking about transistor activity rather than leakage. What about block memories and long run buses? Caches, for example, would have to be excluded from the area equations to come up with the rather lopsided figures they are espousing.

So, turning 99.9% of the silicon into memory blocks is not a bad way to use the space and still keep on shrinking.

EDIT: Hmm, maybe they count memory blocks as being dark ...

evanh

Actually .... need to have a little talk with this David person! Distracting our Chip from doing HubExec goodly, he is!!!

Heater.

Yes, Chip, get back to work or the P2 will remain "Dark Silicon" for ever.



Only joking, have a relaxing Easter.

evanh

evanh wrote: »

Hmm, maybe they count memory blocks as being dark ...

Right, yep, they do seem to do exactly that. But at the same time they also list memory blocks as an example of using the space productively ... but only as cache, they also note adding more cache runs out of puff when it gets too big.

The Propeller would be in heaven with a few hundred megs of HubRAM.

Heater.

So Chip, is the Propeller III going to be a RISC V ISA machine?

evanh

Oi! Save those questions for when Chip asks the next "How many Cogs?" /me shakes fist at Mr Betz

Heater.

Boo, Mr Betz. How could you do this to us?

David Betz

Heater. wrote: »

Boo, Mr Betz. How could you do this to us?

I made sure to mention that this was intended for consideration only for P3 and following. P2 is almost here. Too late for major revisions. :-)

Dave Hein

evanh wrote: »

Actually .... need to have a little talk with this David person! Distracting our Chip from doing HubExec goodly, he is!!!

Yes, I had the same thought. A clear violation of the unwritten "don't bother Chip" treaty. I thought we all had an understanding. Is there a forum moderator in the house? We need to dispense some forum punishment. I suggest subtracting 2000 from his forum post count.

David Betz

Dave Hein wrote: »

Yes, I had the same thought. A clear violation of the unwritten "don't bother Chip" treaty. I thought we all had an understanding. Is there a forum moderator in the house? We need to dispense some forum punishment. I suggest subtracting 2000 from his forum post count.

I would not want to be Chip at this point. We all seem to want to hold him hostage until P2 is done. Lock the door and slip a tray of food under a couple of times a day. Not a way to live. Getting a new P2 FPGA image isn't worth that.

Heater.

David,

Lock the door and slip a tray of food under a couple of times a day. Not a way to live. Getting a new P2 FPGA image isn't worth that.

Yes it is.

David Betz

Heater. wrote: »

David,

Yes it is.

I'm glad you're not my boss.

Dave Hein

David Betz wrote: »

I would not want to be Chip at this point. We all seem to want to hold him hostage until P2 is done. Lock the door and slip a tray of food under a couple of times a day. Not a way to live. Getting a new P2 FPGA image isn't worth that.

I'm almost to the point of agreeing with your view. The P2 is not worth it. Parallax should quit wasting money on it if they are not serious about producing it. If Chip cannot design it in 8 years then there is clearly something wrong with the approach. I'm willing to give them one last chance, but if there is not an FPGA image by June 20, then I feel that I would have to quit wasting my time with Parallax.

David Betz

Dave Hein wrote: »

I'm almost to the point of agreeing with your view. The P2 is not worth it. Parallax should quit wasting money on it if they are not serious about producing it. If Chip cannot design it in 8 years then there is clearly something wrong with the approach. I'm willing to give them one last chance, but if there is not an FPGA image by June 20, then I feel that I would have to quit wasting my time with Parallax.

Hmmm... If people are that close to running out of patience then maybe the locked room is the right solution. :-(

potatohead

Guys, the paper I linked perfectly explains "P2 HOT"

It also contains some great arguments for 16 cogs, the HUB memory design, smart pins, etc...

Those of us who were asking for other blocks, math, SERDES, etc... aren't on a bad path either.

Chip doing some reading and getting some perspective is a good thing.

Dave Hein

potatohead wrote: »

Chip doing some reading and getting some perspective is a good thing.

I assume you are joking since you put a smiley on it. The last thing that Parallax needs at this point is for Chip to read any of the P2 suggestions on the forum. We saw what a debacle that was the last time he did that. IMO Parallax needs to figure out exactly what they want in the P2, and then they need to crank out the Verilog for it. If Chip is too exhausted to do this then they need to hire someone to complete the design or just accept the fact the the P2 will never see the light of day.

nutson

The problems facing designers moving to 20nm and 14nm processes with 10^9 and more transistors can hardly be a threat to Parallax, we are waiting for a chip designed in 180nm. The methods being invented now to handle the problem, limit power consumption and spread power consumption over (even redundant parts) of chips are interesting and every chip designer needs to be aware of them and profit from them.

prof_braino

Dave Hein wrote: »

I'm willing to give them one last chance, but if there is not an FPGA image by June 20, then I feel that I would have to quit wasting my time with Parallax.

Is this a promise? Spring gets more wonderful each year.

Ok, sorry, I'm being a jerk, but I couldn't resist.

rod1963

Well the drama has been going on for 8 years now and still no sign of a P-2. I think it's quite fair to question whether or not we'll ever see a P-2.

evanh

Dave Hein wrote: »

The last thing that Parallax needs at this point is for Chip to read any of the P2 suggestions on the forum. We saw what a debacle that was the last time he did that.

I don't recall any debacle unless you just want to count the robust discussions between forum members. None of which involved Chip, nor anyone from Parallax for that matter.

IMO Parallax needs to figure out exactly what they want in the P2, and then they need to crank out the Verilog for it.

It's really just the total amount of work that takes the time. Be patient.

If Chip is too exhausted to do this then they need to hire someone to complete the design or just accept the fact the the P2 will never see the light of day.

Now that's certainly making some presumptions. While I'm sure Chip enjoys a break now and then I'd be surprised if he's ready to stop. I've certainly noticed Chip, and Ken too, has learnt quite a lot in the last year, some of which has had impact on progress. That's not the actions of someone getting stuck.

rod1963 wrote: »

Well the drama has been going on for 8 years now and still no sign of a P-2. I think it's quite fair to question whether or not we'll ever see a P-2.

No dramas prior to shuttle run. One year tops - And half of that time is people saying, is it ready yet?

Heater.

evanh,

I don't recall any debacle unless you just want to count the robust discussions between forum members. None of which involved Chip, nor anyone from Parallax for that matter.

You don't recall the thousand post long thread where hundreds of ideas were thrashed out with Chip that led to a runaway in the complexity of the design, as feature was piled upon feature, which was finally canned because of thermal issues? That debacle.

At which point Chip went very much quieter here and restarted with a new design that sounds a lot more elegant as far as we know so far.

cgracey

Things are coming together well for the Prop 2.

Last night I got the new transfer/DDS block finished and I hooked it into the cog. It shuttles bytes/word/longs of I/O pin data to/from hub RAM at up to 32 bits per clock. It also drives DACs at those rates and performs DDS/Goertzel operations. It uses a 256x32 look-up RAM for outputting pixel-type and DDS/Goertzel data. All cogs can utilize the full bandwidth without affecting the others. I need to thoroughly test it now and then get onto the next things: hub execution (not much code, but challenging to think about), hub-based CORDIC (straightforward), and smart pins (not hard, but rather open-ended).

I hope that in two months' time, I'll have an FPGA image ready. We are making a final PCB for our Cyclone V -A7 board now. We've already proven it and developed its loader which uses 2Mbps FTDI USB serial talking to a Prop 1. It loads about 35x-70x faster than Quartus' built-in programmer (3 seconds to load straight into the FPGA, 6 seconds to load into flash for cold booting). Our -A7 board will support all 16 cogs and 512KB hub RAM. The DE2-115 will fit ~12 cogs and 256KB hub RAM. All this memory and I/O bandwidth, plus hub exec, is going to be really fun to work with.

Cluso99

Thanks for the update Chip.

David Betz

cgracey wrote: »

Things are coming together well for the Prop 2.

Last night I got the new transfer/DDS block finished and I hooked it into the cog. It shuttles bytes/word/longs of I/O pin data to/from hub RAM at up to 32 bits per clock. It also drives DACs at those rates and performs DDS/Goertzel operations. It uses a 256x32 look-up RAM for outputting pixel-type and DDS/Goertzel data. All cogs can utilize the full bandwidth without affecting the others. I need to thoroughly test it now and then get onto the next things: hub execution (not much code, but challenging to think about), hub-based CORDIC (straightforward), and smart pins (not hard, but rather open-ended).

I hope that in two months' time, I'll have an FPGA image ready. We are making a final PCB for our Cyclone V -A7 board now. We've already proven it and developed its loader which uses 2Mbps FTDI USB serial talking to a Prop 1. It loads about 35x-70x faster than Quartus' built-in programmer (3 seconds to load straight into the FPGA, 6 seconds to load into flash for cold booting). Our -A7 board will support all 16 cogs and 512KB hub RAM. The DE2-115 will fit ~12 cogs and 256KB hub RAM. All this memory and I/O bandwidth, plus hub exec, is going to be really fun to work with.

Thanks for the update. I'm looking forward to the new FPGA image.

evanh

Heater. wrote: »

You don't recall the thousand post long thread where hundreds of ideas were thrashed out with Chip that led to a runaway in the complexity of the design, as feature was piled upon feature, which was finally canned because of thermal issues? That debacle.

I think you'll find the thermal issues were present even in the first shuttle run. The forum requested features were just a bonus.

koehler

evanh wrote: »

I think you'll find the thermal issues were present even in the first shuttle run. The forum requested features were just a bonus.

I thought by the time that 1st shuttle run had been done, there had already been significant addition/lobbying for inclusions already?
Hard to say, but certainly too many cooks in the kitchen.

For some reason though, I'm still concerned with the either inability or unwillingness to simply output a 1 page post on what the current feature set is, and generally where Chip is at.
From a PM POV, I sense rightly or wrongly an apparent lack of interest in prioritizing some simple project communication with the most rabid of all Prop fans on the planet.
Even the most basic of PM's on a project like this, and almost anything smaller, would be having at least a weekly meeting tracking what is done, what isn't, milestone hit or roadblocks encountered, etc,etc.
Any of the knowledgeable engineers at Parallax involved in the P2 should be able to take some meeting minutes, and be able to draft up a simple post which would answer 80-90% of the big question people have.

But maybe I am missing something simple, like Parallax' timeline. Maybe a late Q4, early Q1-2 '16 is what being aimed for?
Thats fine, I'd just hate to see the forum lose some of its more advanced users/volunteers over a simple lack of communication.

evanh

koehler wrote: »

I thought by the time that 1st shuttle run had been done, there had already been significant addition/lobbying for inclusions already?

I've gone back and had a quick squiz just for you - http://forums.parallax.com/showthread.php/125543-Propeller-II-update-BLOG
Turns out the shuttle run was two years ago! Gee, time flies. As far as I can tell Chip and Beau had worked on the design themselves up till that point. There was plenty of banter when Chip released the FPGA images and lots of ideas flying around but the shuttle run was already set at that stage.

Hard to say, but certainly too many cooks in the kitchen.

Just two. Now, just the one. Plus others performing the extra jobs outside of design work.

For some reason though, I'm still concerned with the either inability or unwillingness to simply output a 1 page post on what the current feature set is, and generally where Chip is at.

Progress updates have occurred, you can consider Chips latest above as the one Ken promised. Again, there is so few cooks involved there isn't anyone who specialises in keeping documentation for the design while it's still in flux. That'll come later.

PS: There was documentation on the specs but it went out of date pretty quick.

evanh

Here's a good example of how things played prior to the shuttle run in 2013 - http://forums.parallax.com/showthread.php/125543-Propeller-II-update-BLOG?p=1002844&viewfull=1#post1002844

Chip did the architecture piece by piece and supplied updates as he went. Forum comments were mostly of the what can it do rather than it should do such and such. What's quite notable to me now is there is a full two years of tasters there. Again, longer than I thought.

Heater.

evanh,

Just two. Now, just the one.

This is not the way I saw it. I think koehler is right to say "certainly too many cooks in the kitchen."

I have no idea how this relates to any shuttle run in the time line but there was certainly a lot ideas being presented by forum members, many of which seemed to have been added into the design, over the 300 odd pages of this thread http://forums.parallax.com/showthread.php/141706-Propeller-II[url]

In fact I suggested turning the task switching mechanism from a programmer controlled one to an automatic instruction by instruction thread interleaving one. Which to my amazement Chip implemented with a week or two.
See here:
[/url]http://forums.parallax.com/showthread.php/141706-Propeller-II?p=1117188&viewfull=1#post1117188
and here:
http://forums.parallax.com/showthread.php/141706-Propeller-II?p=1122235&viewfull=1#post1122235

So I could claim that is at least 3 cooks in the kitchen. I am very sure you can find more in that thread.

Feature was piled upon feature until the edifice collapsed.

I'm sure Chip now has a much more elegant design without all that helpful input.