New XMOS chips deliver 4000 MIPS
Leon
Posts: 7,620
These new xCORE-200 devices have been announced by Digi-Key:
Up to 2000 MIPS:
http://media.digikey.com/pdf/Data%20Sheets/XMOS/xCORE-200-XL_PB%281.0%29.pdf
Up to 4000 MIPS:
http://media.digikey.com/pdf/Data%20Sheets/XMOS/xCORE-200-XU_PB%281.0%29.pdf
Strangely, no information is available on the XMOS web site. Digi-Key is their main distributor.
They do look like very useful general-purpose devices. Is there any point to the P2?
Up to 2000 MIPS:
http://media.digikey.com/pdf/Data%20Sheets/XMOS/xCORE-200-XL_PB%281.0%29.pdf
Up to 4000 MIPS:
http://media.digikey.com/pdf/Data%20Sheets/XMOS/xCORE-200-XU_PB%281.0%29.pdf
Strangely, no information is available on the XMOS web site. Digi-Key is their main distributor.
They do look like very useful general-purpose devices. Is there any point to the P2?
Comments
So all the people that hang around this forum have something new to talk about and don't get bored?
So we can run Espruino on a Propeller and have more language wars?
So Tachyon can run really, Really, REALLY fast?
So we can all start designing the P3 FPGA?
See, lots of reasons!!
"The xCORE-200 XL/XLF family includes devices with 8, 10, 12 and 16 cores"
I do wish XMOS would stop saying that. It's not true.
An XMOS core has hardware scheduled threads. It can run 4 at full speed and up to 8 where the speed of each one is now down to half of the 4 thread case.
The XL216 has two cores. Each one which has up to 8 threads. Look at how that block diagram is labelled it says "logical core". i.e. hardware scheduled thread.
Still cool devices though.
http://www.digikey.com/product-search/en?vendor=0&keywords=XLF216-512-FB236-I20-ND
That is the unit price for a tray of 168. One-off prices will be higher.
Wow, isn't that nice of them of have THEIR OWN forum to discuss THEIR products!!!
The XMOS cannot execute code from FLASH. So we are down to 128K or 256K for code and data.
The RAM is split between those "real cores" so for 2 core (16 thread) device is the RAM is limited to 128 or 256K per core depending on device. Still quite good though. Having a big space to store files and static data is of course great.
That 2000MIPs is 1000MIP per real core. If your run all 8 threads on that you get 1000 / 8 / 2 MIPS per thread or 62.5MIPS. That compares to the expected P2 MIPS does it not?
Of course XMOS has a bunch of latched I/O and serdes to boost bit banging speed. Again their I/O pins are split between cores so not as flexible as "any core can use any pin"
If you use that latched/buffered I/O the designation of pins has a bunch of restrictions.
Not many people here are going to want to mess with the BGA package, so by the time they get one on a usable board it will be more expensive.
Look when the P-2 finally shows up in a year or two. It's going to be compared to multicore/minion processor offerings from Xmos, Freescale, NXP, and TI. Or Cypress's PSOC 5.
Xmos just happens to be the most visible one for Prop users at this time.
But direct comparisons and benchmarks will be made whether Parallax likes them or not. Magazine writes ups will no doubt compare the P-2 with other similar products. Prop users shouldn't get upset, it's life in the microprocessor industry.
The XMOS clearly knocks the snot out of the P1 on performance grounds. But my point is that there were/are no other multi-core MCUs in that space.
Recently we have seen ARM SoCs and such sprouting little cores to handle real-time stuff. The PRU's for example. That may be nice but is a different game altogether.
Or have I missed some other interesting devices?
No, do not bother with mentioning the Green Arrays.
Are the tools straightforward, or are they a nightmare? If they are straightforward, I might give it a try; otherwise maybe not.
startKIT is a very low-cost development board:
http://www.xmos.com/startkit
Unlike the P1 and P2, assembly language isn't needed for maximum performance or to achieve deterministic program execution.
The XMOS device can be programmed in C/C++ using a GCC targeted at their architecture. In the same way as prop-gcc.
They also have a a rather clever extension of C, called XC, that makes programming a lot of parallel threads/cores a lot easier. This is also done using GCC.
They have an Eclipse based IDE for all this.
Need a say more, Eclipse is huge, slow and complex and requires one to work at it. Unlike the Spin Tool or Simple IDE for example.
It's pretty good if you are going to be doing XMOS stuff a lot though.
Check out the Freescale offerings that use the eTPU. Freescale was the first company to AFAIK to put a microengine(TPU) on the same piece of silicon as the main cpu (MC68332). Their current offerings that have the eTPU are focused on the automotive industry where they have a large presence.
But they aren't geared to hobbyists, this is why most haven't heard about them.
In the 16 bit arena they have S12 series with the XGATE I/O processor.
However unlike the Prop that has to use most of it's cores to emulate any and all peripherals, these products are loaded with hardware so as not waste processor time. Hence no need to stuff 8 or 16 cores in silicon like Chip did.
TI has their dual core Hercules Safety processors for real time work. The Sitara has it's PRU's.
Infineon has their tri-core processor line of embedded and automotive controllers.
Cypress's PSOC series doesn't do multicore but it has very flexible I/O including analog.
Also all of these devices can also be programmed in C without a nasty performance hit that the P-1 currently suffers from. As for the P-2, it may suffer the same thing if Chip leaves the Cogs as limited as they were in the P-1. No one knows for sure and Chip isn't talking.
Interesting stuff.
How many of those offerings are available to any individual or company that does not want to have to buy in huge quantities?
How easily available are the dev tools? And how easy to use are they? Are they cross-platform and long term sustainable?
How will I know my investment in developing for them will be supported for years to come?
I don't have the time or the will to research all of that. But these are issues that have stymied many good but small scale products in the past.
LLVM was released under the University of Illinois/NCSA Open Source License.
I'm trying to extract what is different ?
The old parts were 64K ? , so these new ones have more RAM,
They 'forgot' to mention MHz so it is not clear what clock speed the new parts hit.
1000 MIPS hints at 125MHz equiv clock per core, which is not that much faster than the older parts.
Anyone know what the timer / measurement resolution is on these new parts ?
It does move the goal posts on the P2, and makes 512K (which was a leading RAM size) now just me-too.
P2 certainly cannot shrink RAM size now.
128 i/o edges ahead of P2.
It is also now establishing a trend of Flash on Board, - the NUC505 does a very similar thing, with a Serial Flash part in the corner. (stacked die?)
Addit:
Google uncovers this other family too
http://media.digikey.com/pdf/Data%20Sheets/XMOS/xCORE-200-XU_PB%281.0%29.pdf
That XU part is even larger
* Integrated USB 2.0 PHY for high and full-speed host and device operation.
* Up to 1024KB on-board memory for demanding applications.
* Up to 32 'Logical' cores
* from TQFP64 [33io] to FB324 [208 io]
So a family from 128K RAM, TQFP64 for simpler tasks, up to a FB324 with HS USB, and 2048 FLASH is quite a bit of market coverage.
Thanks for sharing.
They max out at 4 cores. Each with 8 hardware time sliced threads (which XMOS call "logical cores"). See the diagram in the PDFs linked to above.
Due to the pipelined architecture 4 such threads on a core will run at full speed. But use all 8 threads on a core and the speed of all of them is halved.
Still, pretty quick though.
Are there any nice little dev boards for XMOS devices now a days?
Seems the little red original dev boards that I have were phased out and replaced with "slice kits" or whatever they were called. I did not much like the look of them.
Is that still true of the new parts ?
So that means 32 'cores' have the same 'mips' as 16 'cores'.
If those 32 are 50% reduced, does that mean Peak MIPS is now 250Mhz ? (or is it limited to 125MHz ?)
( High end DSPs can hit 250MHz ... )
Somebody will have to install their dev tool and do some timing analysis with different numbers of threads on a core to demonstrate the effect. (Their compiler can tell you how long a code sequence takes to run, you don't have to actually run it)
I would do it myself but I don't think I have room on this SSD here for the monster Eclipse install required.
Question 2: What is the motive behind this behavior?
Question 3: Is there UPS delivery to Antelope Valley?