I'm under no illusion that I'll ever get one, but for the record, the chip I'd really like is...
16 x 100 MIPS cores (cores 1-16) each with 4k of 32-bit longs for registers, no hubexec, smart pins as previously described
1 additional (identical) core 0 with no IO but with hubexec from central memory
256k of central memory accessed in a strict round robin core0, core1, core0, core2, core0, core3....
central cordic and central big multiplier
that's it, no slot allocation, no tables, no complicated schemes.
I hear the cry "but the core only has 9-bit address fields" to which I reply "so what, that's the last processor, the proposed one bears no resemblance to it, and existing objects won't run without modification anyway."
Plus a decent IDE C compiler, for which I'd pay money, and a set of known working soft-peripherals to get designs off the ground quickly.
The reality is that I'll not see one of those nor any other silicon in the wild for at least a year. Shame really. But, on the up side I can buy M4 based boards now for less than the projected cost of a P16X64A chip and if I bought a DE0-nano I can fit 12 NIOS-IIs in it.