What are the standard clkfreq values above 80MHz?

KyeKye
edited July 2010 in Propeller 1 Vote Up0Vote Down
I'm working on a new VGA object and I figured out pretty much that you need to have an exact frequency output to get all monitors to lock at 60Hz. That screen slowly fadding to white problem·that others have had comes actually from the fact that by trying to calculate the VGA frequency output with integer math·you do not get an exact result that is usable for the pixel clock.

So... I'm just going to use precomputed·values and then·use a different one for each clock frequency.

So far I have 80Mhz, 100Mhz, and 96Mhz as supported values. Are there any more popular clock frequencies that people use?

Honestly, I'd rather not hardcode this but... I need 64 bit math to get a proper result and I'm not really that good at breaking stuff up yet.

What I need to do is this....··((6,293,750 * 4,294,967,296) / clkfreq)

If I had 64 bit math the result would then come out to 337,893,130... The exact answer I need is 337,893,131 so I need to round up after the divide.

Thanks for your help,

Oh, and about the screen slowly fadding to white error. The reason this happens is because the pixel clock is not as high as it needs to be for the number of pixels you are pumping out to the screen. Because of this, each frame to the monitor is longer than it should be and the monitor will probably see like a 59Hz signal instad of 60Hz. This causes the monitor to basically get confused. So, you can fix the problem by either increasing the pixel clock frequency until it matches the number of pixels sent to the screen or you can reduce the number of pixels sent to the screen.

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Nyamekye,

Post Edited (Kye) : 7/1/2010 6:22:16 PM GMT
Nyamekye,
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  • 30 Comments sorted by Votes Date Added
  • edited July 2010 Posts: 0Vote Up0Vote Down
    You have the three frequencies that I use smile.gif

    I especially like 96mhz since the xtals are so much cheaper than the 6.250 xtals.
    [The Bug Stops Here]
  • edited July 2010 Posts: 0Vote Up0Vote Down
    Hi Kye.

    I run so many different Frequencies that drivers that are not reprogramming have not any use for me.



    Regards

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    Sapieha
    Regards
    Sapieha
    _____________________________________________________
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  • edited July 2010 Posts: 0Vote Up0Vote Down
    10.4857600 MHz is poplar around here[noparse]:)[/noparse]

    That's a 6.553600 MHz XTAL which I have a few of. The fastest I have pushed the TriBladeProp so far.

    For BST users use #defines to set the frequency at build time and issue a warning if none is defined. Put the formula clearly in the code.

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  • KyeKye
    edited July 2010 Posts: 2,200Vote Up0Vote Down
    So.... suggestions on how to do 64 bit math? =) Then I could fix this problem.

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    Nyamekye,
    Nyamekye,
  • edited July 2010 Posts: 0Vote Up0Vote Down
    Kye said...
    What I need to do is this.... ((6,293,750 * 4,294,967,296) / clkfreq)
    Are both numbers in the numerator constant?
    If so, the numerator is evenly divisible by 100,000.
    But that would be too easy ....

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  • KyeKye
    edited July 2010 Posts: 2,200Vote Up0Vote Down
    Yes both numbers in the numerator are constants. I just have to divide by a changing clkfreq. But I need the most exact result possible rounded up.

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    Nyamekye,
    Nyamekye,
  • edited July 2010 Posts: 0Vote Up0Vote Down
    Phil put up some spin code umath.spin sometime - can't find the pointer at the moment - 64bit unsign math, multi/div/add. div is 64 bit /32 bit -> 32bit.
    http://obex.parallax.com/objects/415/
    ·
  • edited July 2010 Posts: 0Vote Up0Vote Down
    Spending great effort to support anything other than reasonable frequencies is very nice of you.

    People can use any frequency they like I guess as long as they realize what they're doing, but frequencies with big round numbers are commonly available. How much do those other frequencies cost for production? Is there really a great return in using them (other than that's what happened to be laying on the hobby workbench)?

    Cheers,
    --Steve

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  • KyeKye
    edited July 2010 Posts: 2,200Vote Up0Vote Down
    I just want my code to be as flexible as possible. I don't mind taking up extra space for that. I'm trying very hard to avoid magic numbers.

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    Nyamekye,
    Nyamekye,
  • KyeKye
    edited July 2010 Posts: 2,200Vote Up0Vote Down
    Okay, this solves it.

        pinGroup := constant(25_175_000 / 4)
        frequencyState := 1
        
        repeat 32
          pinGroup <<= 1                        
          frequencyState <-= 1
          if(pinGroup => clkfreq)
            pinGroup -= clkfreq
            frequencyState += 1  
    

    pinGroup is a variable I'm resusing and frequencyState is the output.

    Rather nasty however. I would have liked a one line solution.

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    Nyamekye,
    Nyamekye,
  • edited July 2010 Posts: 0Vote Up0Vote Down
    Kye, I use 104MHz (6MHz * 16) because 6.5MHz xtals are cheap and readily available at DigiKey. Also I intend going to 108MHz (13.5MHz * 8) in the future as these are also readily available. To use these, a good pcb layout is mandatory. Also, Bill and others are using his 6.25MHz * 16 (100MHz) xtals.

    I did some work on calculations for my latest 1pin TV driver which uses the compiler to do the hard work in calculations which saves space in the actual code. It no doubt has the same inaccuracies due to rounding as you have found, but it may be worth a look for you. I was not originally aware I could create these calculations using the compiler.

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  • edited July 2010 Posts: 0Vote Up0Vote Down
    Kye, a double precision accumulator is not necessary. This is a ratio calculation of the form
    f = x * a/b where x here is 232.

    a=NCO frequency desired = 6_293_750 in your original example
    b=cpu CLKFREQ = 80_000_000 for example, but this is a variable too.

    PRI frqVal(a, b) : f      ' return f = a/b * 2^32, given a<b, a<2^30, b<2^30
      repeat 32                           ' 32 bits
         a <<= 1
         f <<= 1
         if a => b
            a -= b
            f++
    



    returns f = 337_893_130 in your example with a=6_293_750 and b=80_000_000. That f is what goes into the frqa register for the NCO. The multiplication by 232 happens automatically in the algorithm.

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    Tracy Allen
    www.emesystems.com
  • edited July 2010 Posts: 0Vote Up0Vote Down
    Crazy how similar Kye's and Tracy's algorithms are! It would be interesting to know how each of you gentlemen arrived at your solutions. Care to elaborate?
  • edited July 2010 Posts: 0Vote Up0Vote Down
    Here is the code derived from Chip's code that I used to calculate the frqa counter for NTSC and PAL TV.
    PRI Setforxtalfreq : f | Freq, PropFreq, shift
    '' Return frqa value for the current clkfreq
    '' Derived from CTR.SPIN by Chip Gracey
      Freq := ocolsfrq * ocols * 8                          'frequency required
      shift := 4 - >|((Freq - 1) / 1_000_000)               'determine shift 
      PropFreq := CLKFREQ
      if shift > 0                                          'if shift, pre-shift Freq or PropFreq left
        Freq <<= shift                                      'to maintain significant bits while
      if shift < 0                                          'insuring proper result
        PropFreq <<= -shift
     
      repeat 32                                             'perform long division of Freq / PropFreq
        f <<= 1
        if Freq => PropFreq
          Freq -= PropFreq
          f++                                               'compute frqa value
        Freq <<= 1
     
    

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  • KyeKye
    edited July 2010 Posts: 2,200Vote Up0Vote Down
    I just took code from the synth object in the propeller library. Then modified it to add 1 to the final answer.

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    Nyamekye,
    Nyamekye,
  • edited July 2010 Posts: 0Vote Up0Vote Down
    Oh, that's what "frequencyState := 1" and the "<-=" are for! Clever!
  • KyeKye
    edited July 2010 Posts: 2,200Vote Up0Vote Down
    Takes up no extra code space too.

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    Nyamekye,
    Nyamekye,
  • edited July 2010 Posts: 0Vote Up0Vote Down
    I've had a DIP32 prop running off of a scavenged 7.00 MHz crystal x16·(112MHz) with no problems, but if i recall right, the various guts in the P8x32A silicon start malfunctioning around 128MHz, but as always, i could be (and probably am) wrong.
    Tracy Allen said...
    Kye, a double precision accumulator is not necessary. This is a ratio calculation of the form
    f = x * a/b where x here is 232.

    a=NCO frequency desired = 6_293_750 in your original example
    b=cpu CLKFREQ = 80_000_000 for example, but this is a variable too.

    PRI frqVal(a, b) : f      ' return f = a/b * 2^32, given a<b, a<2^30, b<2^30
      repeat 32                           ' 32 bits
         a <<= 1
         f <<= 1
         if a => b
            a -= b
            f++
    



    returns f = 337_893_130 in your example with a=6_293_750 and b=80_000_000. That f is what goes into the frqa register for the NCO. The multiplication by 232 happens automatically in the algorithm.

    It took me a few minutes to understand what was going on here. I learned not to long ago in my AEES course how binary math is done, and how it is accomplished within hardware.. the repeat loop to multiply is beautiful, because binary multiply can be·done as a series of additions. Its funny the more things i learn in colledge, the more i see implimented in the code i read.

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  • edited July 2010 Posts: 0Vote Up0Vote Down
    I haven't ran into problems at 200 Mhz (25 x 8) but just started using this setup a couple days ago. I haven't had any success higher than that though.
  • edited July 2010 Posts: 0Vote Up0Vote Down
    micronewb,

    I'm dubious of your "25x8" claim. You might be getting programs to run at that setting, but your clock speed won't be 200MHz. The reason is that the PLL's free-running frequency tops out before 256MHz (at 16x), which means 128MHz at 8x. Basically, the PLL can't lock onto your crystal, since its frequency is way too high, and is free-running instead. According to the specs, the crystal frequency should be between 4MHz and 8MHz, although reliable operation can be had at 10MHz.

    -Phil
    “Impossible is just a big word thrown around by small men who find it easier to live in the world they’ve been given than to explore the power they have to change it. Impossible is not a fact. It’s an opinion. Impossible is not a declaration. It’s a dare. Impossible is potential. Impossible is temporary. Impossible is nothing.” –Muhammad Ali
  • edited July 2010 Posts: 0Vote Up0Vote Down
    phil, I agree this seems strange and I wish i could send u an oscilliscope pic but mine tops out at 100 MHz. So what I am doing is blinking two LEDS from two separate cogs. One is using the standard waitcnt(clkfreq + cnt) to blink 1 sec, the other is waitcnt(200_000_000 + cnt) and they blink in sync. I could be missing something so please correct if this is not right.
  • edited July 2010 Posts: 0Vote Up0Vote Down
    clkfreq is just a value put into a register by the compiler -- in your case 200_000_000. It is not an actual frequency measurement. So, yes, your LEDs will be in sync, but slower than 1Hz. Since you have a scope, try outputting a frequency of 1KHz and see what the actual frequency is.

    -Phil
    “Impossible is just a big word thrown around by small men who find it easier to live in the world they’ve been given than to explore the power they have to change it. Impossible is not a fact. It’s an opinion. Impossible is not a declaration. It’s a dare. Impossible is potential. Impossible is temporary. Impossible is nothing.” –Muhammad Ali
  • edited July 2010 Posts: 0Vote Up0Vote Down
    well played phil, but this brings up a question. with a 25 MHz crystal and X8 multiplier it runs right at 121 MHz, how is this working? if the PLL can't lock the frequency then it should be running at 25 MHz or am I totally messed up on that? Not much experience with PLL...obviously
  • edited July 2010 Posts: 0Vote Up0Vote Down
    The PLL has its own VCO (voltage-controlled oscillator). This oscillator is divided by 16 and phase-locked to the crystal frequency. (So, you see, PLLx8 is really PLL/2.) But it can only oscillate so fast on its own. If it can't lock onto the crystal, it just runs at it's top, free-running speed which, in your case, is 242MHz.

    -Phil
    “Impossible is just a big word thrown around by small men who find it easier to live in the world they’ve been given than to explore the power they have to change it. Impossible is not a fact. It’s an opinion. Impossible is not a declaration. It’s a dare. Impossible is potential. Impossible is temporary. Impossible is nothing.” –Muhammad Ali
  • edited July 2010 Posts: 0Vote Up0Vote Down
    good explanation thanks! i guess i will surrender to around 128 MHz is as fast as it can go.
  • edited July 2010 Posts: 0Vote Up0Vote Down
    Phil Pilgrim (PhiPi) said...
    The PLL has its own VCO (voltage-controlled oscillator). This oscillator is divided by 16 and phase-locked to the crystal frequency. (So, you see, PLLx8 is really PLL/2.) But it can only oscillate so fast on its own. If it can't lock onto the crystal, it just runs at it's top, free-running speed which, in your case, is 242MHz.

    -Phil
    Out of curiosity, does this mean I could run the prop with the crystal pins as no-connects, specify a '_clkmode = xtal1 + pll8x', and end up with, in effect, a 'RCSUPERFAST'? Knowing, of course, that I no longer have any timing precision.

    Jonathan

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  • edited July 2010 Posts: 0Vote Up0Vote Down
    'Dunno. Try it! Of course, since the "crystal" is oscillating at 0Hz, you may end up discovering the VCO's low-end frequency!

    -Phil
    “Impossible is just a big word thrown around by small men who find it easier to live in the world they’ve been given than to explore the power they have to change it. Impossible is not a fact. It’s an opinion. Impossible is not a declaration. It’s a dare. Impossible is potential. Impossible is temporary. Impossible is nothing.” –Muhammad Ali
  • KyeKye
    edited July 2010 Posts: 2,200Vote Up0Vote Down
    So, if you use an external oscilator how fast could you go with cooling...

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    Nyamekye,
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  • edited July 2010 Posts: 0Vote Up0Vote Down
    Coley holds the record for uncooled speed. He topped out IIRC ~148MHz using an external oscillator and overvoltage. On a standard 3V3 Sapieha has had my TriBlade running at 120MHz with a 15MHz x8 for many months (if still running it is over a year). Chip said the PLL tops out at around 14.5MHz and it sort of confirms what I found with the RamBlade. IIRC I got 14.31818MHz x8 running. 13.5MHz x8 seems to run fine too. 7.3xxMHz x16 fails.
    From my tests I believe the DIP is more tolerant - don't ask me why as I haven't a clue.

    As for cooling, theoretically it should go faster, but the chip is not getting hot.

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    · Emulators: CPUs Z80 etc; Micros Altair etc;· Terminals·VT100 etc; (Index) ZiCog (Z80) , MoCog (6809)·
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