'************************************* '* z80_emu v0.0 * '* An emulation of the Zilog z80 * '* (C) 2009 Michael Rychlik * '************************************* ' 'v0.0 - 29 Feb 2009 - Original version ' CON '8080 Program Status Word bits sign_bit = %10000000 zero_bit = %01000000 aux_bit = %00010000 parity_bit = %00000100 carry_bit = %00000001 'I/O control block commands io_cmd_out = $01 io_cmd_in = $02 VAR long cog PUB start(cpu_params) : okay | reg_base, io_base '' Start CPU simulator - starts a cog '' returns false if no cog available '' '' cpu_par_params is a pointer to CPU parameter list stop reg_base := LONG[cpu_params] c_reg := reg_base b_reg := reg_base + 1 e_reg := reg_base + 2 d_reg := reg_base + 3 l_reg := reg_base + 4 h_reg := reg_base + 5 psw_reg := reg_base + 6 a_reg := reg_base + 7 c_reg_alt := reg_base + 8 b_reg_alt := reg_base + 9 e_reg_alt := reg_base + 10 d_reg_alt := reg_base + 11 l_reg_alt := reg_base + 12 h_reg_alt := reg_base + 13 psw_reg_alt := reg_base + 14 a_reg_alt := reg_base + 15 im_reg := reg_base + 16 ix_reg := reg_base + 18 iy_reg := reg_base + 20 sp_reg := reg_base + 22 pc_reg := reg_base + 24 ram_base := LONG[cpu_params + 4] ram_size := LONG[cpu_params + 8] rom_base := LONG[cpu_params + 12] rom_address := LONG[cpu_params + 16] io_base := LONG[cpu_params + 20] io_base := LONG[cpu_params + 20] io_command := io_base io_port := io_base + 4 io_data := io_base + 8 cpu_control := LONG[cpu_params + 24] op_reg := LONG[cpu_params + 28] object_base := @@0 'Set up the base address of this object okay := cog := cognew(@enter, 0) + 1 'Start emulator in a new COG PUB stop '' Stop CPU simulator - frees a cog if cog cogstop(cog~ - 1) DAT '--------------------------------------------------------------------------------------------------------- org 0 '--------------------------------------------------------------------------------------------------------- enter mov dira, heartbeat_pin 'Set Pins to output add dispatch_tab_addr, object_base 'Fixup this object offset to HUB real address '--------------------------------------------------------------------------------------------------------- 'Instruction fetch loop starts here undocumented fetch 'call #break mov address, pc call #read_memory_byte 'Read the instruction byte there add pc, #1 'Increment the program counter xor outa, heartbeat_pin xor outa, heartbeat_pin mov disp_ptr, data_8 'Dispatch table look up shl disp_ptr, #2 'Mul by 4 to get a LONG offset into the table add disp_ptr, dispatch_tab_addr 'Index into table rdlong vector, disp_ptr 'Read the instruction handlers vectors (3 per long) jmp vector 'Jump to the instruction handler vect_2 shr vector, #9 'shift to 2nd vector jmp vector vect_3 shr vector, #9 'shift to 3rd vector jmp vector pc long 0 '8080's Pogram Conter sp long 0 '8080's Stack pointer cpu_control long 0 heartbeat_pin long %00000000_00000001_00000000_00000000 op long 0 dispatch_tab_addr long @dispatch_table object_base long 0-0 'HUB address of this object vector long 0 disp_ptr long 0 '--------------------------------------------------------------------------------------------------------- '--------------------------------------------------------------------------------------------------------- break wrword pc, pc_reg mov data_16, #0 wrword data_16, cpu_control :break rdword data_16, cpu_control cmp data_16, #0 wz if_z jmp #:break break_ret ret '--------------------------------------------------------------------------------------------------------- '--------------------------------------------------------------------------------------------------------- 'Data Source Functions get_b rdbyte data_8, b_reg jmp #vect_2 get_c rdbyte data_8, c_reg jmp #vect_2 get_d rdbyte data_8, d_reg jmp #vect_2 get_e rdbyte data_8, e_reg jmp #vect_2 get_h rdbyte data_8, h_reg jmp #vect_2 get_l rdbyte data_8, l_reg jmp #vect_2 get_a rdbyte data_8, a_reg 'mov a_reg, data_8 jmp #vect_2 get_f rdbyte data_8, psw_reg jmp #vect_2 get_bc rdword data_16, b_reg jmp #vect_2 get_de rdword data_16, d_reg jmp #vect_2 get_hl rdword data_16, h_reg jmp #vect_2 get_af rdword data_16, a_reg jmp #vect_2 get_sp rdword data_16, sp_reg jmp #vect_2 get_pc rdword data_16, pc_reg jmp #vect_2 get_m get_memory_hl rdword address, h_reg call #read_memory_byte jmp #vect_2 get_memory_bc rdword address, b_reg call #read_memory_byte jmp #vect_2 get_memory_de rdword address, d_reg call #read_memory_byte jmp #vect_2 'Read a BYTE from location given by "pc" of 8080 RAM into byte data_8 and increment pc get_immediate_byte mov address, pc call #read_memory_byte add pc, #1 jmp #vect_2 'Read a WORD from location given by "pc" of 8080 RAM into byte data_16 and pc = pc + 2 get_immediate_word mov address, pc call #read_memory_word add pc, #2 jmp #vect_2 test_flag_true test_flag_false return_conditional return_unconditional rdword sp, sp_reg mov address, sp call #read_memory_byte 'Read the low byte mov pc, data_8 ror pc, #8 add address, #1 call #read_memory_byte 'Read the high byte or pc, data_8 rol pc, #8 add sp, #2 wrword sp, sp_reg jmp #fetch jump_conditional jump_unconditional mov address, pc call #read_memory_byte 'Read the low byte mov pc, data_8 ror pc, #8 add address, #1 call #read_memory_byte 'Read the high byte or pc, data_8 rol pc, #8 jmp #fetch call_conditional call_unconditional mov data_16, pc add data_16, #2 call #push jmp #jump_unconditional restart mov data_16, pc call #push shr vector, #9 mov pc, vector jmp #fetch push rdword sp, sp_reg sub sp, #2 mov address, sp call #write_memory_word wrword sp, sp_reg push_ret ret pop rdword sp, sp_reg mov address, sp call #read_memory_byte 'Read the low byte mov data_16, data_8 ror data_16, #8 add address, #1 call #read_memory_byte 'Read the high byte or data_16, data_8 rol data_16, #8 add sp, #2 wrword sp, sp_reg pop_ret ret z80_CB 'Z80, CB Prefix z80_DD 'Z80, DD Prefix z80_ED 'Z80, ED Prefix z80_FD 'Z80, FD Prefix in out mov address, pc call #read_memory_byte add pc, #1 wrbyte data_8, io_port rdbyte data_8, a_reg 'Write output data from accumulator wrbyte data_8, io_data mov data_8, #io_cmd_out 'Set I/O command to OUT wrbyte data_8, io_command ':io_wait rdbyte data_8, io_command wz ' if_nz jmp :io_wait { mov data_16, #0 '\ DEBUG CODE wrword data_16, cpu_control '/ :halt rdword data_16, cpu_control '\ cmp data_16, #0 wz ' | DEBUG CODE if_z jmp #:halt '/ } jmp #fetch store_a_direct mov address, data_16 rdbyte data_8, a_reg call #write_memory_byte jmp #fetch load_a_direct mov address, data_16 call #read_memory_byte wrbyte data_8, a_reg jmp #fetch store_hl_direct mov address, data_16 rdword data_16, h_reg call #write_memory_word jmp #fetch load_hl_direct mov address, data_16 call #read_memory_word wrword data_16, h_reg jmp #fetch z80_exx get_ixy 'FIXME for z80 jmp #fetch get_mem_ixy_idx 'FIXME for z80 jmp #vect_2 '--------------------------------------------------------------------------------------------------------- '--------------------------------------------------------------------------------------------------------- 'Data Destination Functions put_b wrbyte data_8, b_reg jmp #fetch put_c wrbyte data_8, c_reg jmp #fetch put_d wrbyte data_8, d_reg jmp #fetch put_e wrbyte data_8, e_reg jmp #fetch put_h wrbyte data_8, h_reg jmp #fetch put_l wrbyte data_8, l_reg jmp #fetch put_a wrbyte data_8, a_reg 'mov a_reg, data_8 jmp #fetch put_f wrbyte data_8, psw_reg jmp #fetch put_bc wrword data_16, b_reg jmp #fetch put_de wrword data_16, d_reg jmp #fetch put_hl wrword data_16, h_reg jmp #fetch put_af wrword data_16, a_reg jmp #fetch put_sp wrword data_16, sp_reg jmp #fetch put_pc wrword data_16, pc_reg jmp #fetch put_m put_memory_hl rdword address, h_reg call #write_memory_byte jmp #fetch put_memory_bc rdword address, b_reg call #write_memory_byte jmp #fetch put_memory_de rdword address, d_reg call #write_memory_byte jmp #fetch put_ixy 'FIXME for z80 jmp #fetch put_mem_ixy_idx 'FIXME for z80 jmp #fetch '--------------------------------------------------------------------------------------------------------- '--------------------------------------------------------------------------------------------------------- 'Memory Access Functions 'Read a BYTE from location given by "address" of 8080 RAM into byte data_8 read_memory_byte cmp address, ram_size wc,wz 'Is the given address within the RAM range ? if_b jmp #:read_ram call #read_rom jmp read_memory_byte_ret :read_ram mov hub_pointer, ram_base 'Point to the RAM add hub_pointer, address 'Add address offset rdbyte data_8, hub_pointer 'Read the byte from there read_memory_byte_ret ret read_rom cmp address, rom_start wc,wz 'Is the given address within the ROM range ? if_b jmp read_rom_ret 'address below rom_base => return with "data" undefined mov rom_address, address sub rom_address, rom_start 'address becomes offset into ROM from start of ROM mov hub_pointer, rom_base 'Point to the ROM add hub_pointer, rom_address 'Add address offset rdbyte data_8, hub_pointer 'Read the byte from there read_rom_ret ret 'Return 'Write the BYTE data_8 to location given by "address" write_memory_byte cmp address, ram_size wc,wz 'Is the given address within the RAM range ? if_b mov hub_pointer, ram_base 'Point to the RAM if_b add hub_pointer, address 'Add address offset if_b wrbyte data_8, hub_pointer 'Write the byte there write_memory_byte_ret ret 'Read a WORD from location given by "address" of 8080 RAM into byte data_16 read_memory_word call #read_memory_byte 'Read the low byte mov data_16, data_8 ror data_16, #8 add address, #1 call #read_memory_byte 'Read the high byte or data_16, data_8 rol data_16, #8 read_memory_word_ret ret 'Write the WORD data_16 to location given by "address" write_memory_word mov data_8, data_16 call #write_memory_byte 'Write the LOW byte shr data_8, #8 add address, #1 call #write_memory_byte write_memory_word_ret ret 'The following configuration "constants" set from COG PARameters. ram_base long 0-0 'HUB address of the 8080 RAM area ram_size long 0-0 'Length in bytes of available 8080 RAM rom_base long 0-0 'HUB address of the BOOT ROM image rom_start long 0-0 'ROM starts at this address in 8080 space rom_address long 0-0 '8080 RAM read/write vars. hub_pointer long 0 'Pointer into HUB RAM address long 0 'Address param for read/write funcs data_8 long 0 'Data bytes read into here data_16 long 0 'Data words read into here '--------------------------------------------------------------------------------------------------------- '--------------------------------------------------------------------------------------------------------- '8080 Operation Functions null_op jmp #vect_3 'FIXME we should never need this !!! set_carry rdbyte flags, psw_reg or flags, #carry_bit 'Set Carry Flag wrbyte flags, psw_reg jmp #fetch complement_carry rdbyte flags, psw_reg xor flags, #carry_bit 'Complement Carry Flag wrbyte flags, psw_reg jmp #fetch complement_byte xor data_8, #$FF jmp #vect_3 increment_byte mov aux, data_8 'Keep a copy for AUX carry determination add data_8, #1 'Do the increment inc_dec_flags rdbyte flags, psw_reg xor aux, data_8 'AUX carry ? test aux, #aux_bit wz muxnz flags, #aux_bit and data_8, #$FF wz, wc muxz flags, #zero_bit muxnc flags, #parity_bit test data_8, #128 wz muxnz flags, #sign_bit wrbyte flags, psw_reg jmp #vect_3 decrement_byte mov aux, data_8 'Keep a copy for AUX carry determination sub data_8, #1 'Do the decrement jmp #inc_dec_flags 'Set the flags daa rdbyte flags, psw_reg mov nibble, data_8 'Isolate low nibble of accumulator and nibble, #$0F cmp nibble, #10 wc 'Test for greater than 9 test flags, #aux_bit wz 'Test auxillary carry if_nz_or_nc add data_8, #$06 'Add 6 to accumulator if greater than 9 or AUX carry add nibble, #6 'Check for AUX carry from low nibble test nibble, #%00010000 wz muxnz flags, #aux_bit 'and set AUX flag if so. mov nibble, data_8 'Isolate high nibble of accumulator shr nibble, #4 cmp nibble, #10 wc 'Test for greater than 9 test flags, #carry_bit wz 'Test carry flag if_nz_or_nc add data_8, #$60 'Add (6 << 4) to accumulator if greater than 9 or carry test data_8, #$100 wz 'Check for 8 bit carry out if_nz or flags, #carry_bit 'Set carry flag if so (N.B. Do NOT clear carry if not so) and data_8, #$FF wz, wc muxz flags, #zero_bit 'Set 8080 zero flag from props zero muxnc flags, #parity_bit test data_8, #128 wz muxnz flags, #sign_bit wrbyte flags, psw_reg jmp #vect_3 alu_add rdword alu, a_reg 'Load A and Flags mov flags, alu shr alu, #8 mov aux, alu 'Take a copy of alu before operation for AUX carry determination add alu, data_8 'Do the op jmp #alu_arith_flags alu_add_with_carry rdbyte alu, a_reg rdbyte flags, psw_reg 'Load flags mov aux, alu 'Take a copy of alu before operation for AUX carry determination test flags, #carry_bit wc 'Set prop's carry from 8080 carry flag addx alu, data_8 'Do the op jmp #alu_arith_flags alu_sub rdword alu, a_reg 'Load A and Flags mov flags, alu shr alu, #8 mov aux, alu 'Take a copy of alu before operation for AUX carry determination sub alu, data_8 'Do the op alu_arith_flags test alu, #$100 wz 'Determine the carry flag muxnz flags, #carry_bit xor aux, data_8 xor aux,alu 'Determine the auxillary carry flag test aux, #aux_bit wc muxc flags, #aux_bit and alu, #$FF wz, wc 'Set zero, sign and parity flags from alu content muxz flags, #zero_bit 'Set 8080 zero flag from props zero muxnc flags, #parity_bit 'That "and" above gives parity in props carry flag test alu, #128 wz 'Top bit is sign muxnz flags, #sign_bit wrbyte flags, psw_reg 'Unload flags mov data_8, alu jmp #vect_3 alu_sub_with_borrow rdword alu, a_reg 'Load A and Flags mov flags, alu shr alu, #8 mov aux, alu 'Take a copy of alu before operation for AUX carry determination test flags, #carry_bit wc 'Set prop's carry from 8080 carry flag subx alu, data_8 'Do the op jmp #alu_arith_flags alu_and rdword alu, a_reg 'Load A and Flags mov flags, alu shr alu, #8 and alu, data_8 wz, wc 'Do the AND and get flags or flags, #aux_bit 'AND always sets AUX flag (8085) alu_logic_flags andn flags, #carry_bit 'Logic ops always clear carry flag muxz flags, #zero_bit 'Set Z flag muxnc flags, #parity_bit 'Set Parity flag test alu, #128 wz 'Get sign of result muxnz flags, #sign_bit 'Set sign flag accordingly wrbyte flags, psw_reg 'Unload flags mov data_8, alu jmp #vect_3 alu_xor rdword alu, a_reg 'Load A and Flags mov flags, alu shr alu, #8 xor alu, data_8 wz, wc 'Do the XOR and get flags andn flags, #aux_bit 'XOR always clears AUX flag jmp #alu_logic_flags alu_or rdword alu, a_reg 'Load A and Flags mov flags, alu shr alu, #8 or alu, data_8 wz, wc 'Do the OR and get flags andn flags, #aux_bit 'OR always clears AUX flag jmp #alu_logic_flags alu_rlc mov alu, data_8 rdbyte flags, psw_reg shl alu, #1 'Shift accumulator left by one test alu, #%1_0000_0000 wz 'Move any 8 bit carry out bit into acc LSB muxnz alu, #1 muxnz flags, #carry_bit 'Set carry flag from 8 bit overflow write_af_then_done wrbyte flags, psw_reg mov data_8, alu jmp #vect_3 alu_rrc mov alu, data_8 rdbyte flags, psw_reg shr alu, #1 wc 'Shift accumulator right by one muxc alu, #%10000000 'Move props carry to acc. MSB muxc flags, #carry_bit 'Set carry flag from props carry jmp #write_af_then_done alu_ral mov alu, data_8 rdbyte flags, psw_reg shl alu, #1 'Shift accumulator left by one test flags, #carry_bit wz 'Set acc. LSB from carry flag muxnz alu, #1 test alu, #%1_0000_0000 wz 'Set carry flag from 8 bit overflow muxnz flags, #carry_bit jmp #write_af_then_done alu_rar mov alu, data_8 rdbyte flags, psw_reg shr alu, #1 wc 'Shift accumulator right by one test flags, #carry_bit wz 'Set acc. MSB from carry flag muxnz alu, #%10000000 muxc flags, #carry_bit 'Set carry flag from props carry out jmp #write_af_then_done alu_sla 'FIXME for Z80 alu_sra alu_srl alu_bit alu_res alu_set increment_word add data_16, #1 jmp #vect_3 decrement_word sub data_16, #1 jmp #vect_3 double_add rdword alu, h_reg rdbyte flags, psw_reg add alu, data_16 test alu, mask_bit_16 wz muxnz flags, #carry_bit wrbyte flags, psw_reg mov data_16, alu jmp #vect_3 double_add_ixy 'FIXME for z80 load_byte call #read_memory_byte 'Load data_8 from the byte at "address" jmp #vect_3 store_byte call #write_memory_byte 'Store data_8 to the byte at "address" jmp #vect_3 load_word call #read_memory_word 'Load data_16 from the word at "address" jmp #vect_3 store_word call #write_memory_word 'Store data_16 to the word at "address" jmp #vect_3 '--------------------------------------------------------------------------------------------------------- 'Misc variables alu long 0 flags long 0 aux long 0 nibble long 0 mask_bit_16 long $0001_0000 '--------------------------------------------------------------------------------------------------------- 'Pointers to 8080/Z80 registers in HUB RAM c_reg long 0 b_reg long 0 e_reg long 0 d_reg long 0 l_reg long 0 h_reg long 0 psw_reg long 0 a_reg long 0 c_reg_alt long 0 b_reg_alt long 0 e_reg_alt long 0 d_reg_alt long 0 l_reg_alt long 0 h_reg_alt long 0 psw_reg_alt long 0 a_reg_alt long 0 im_reg long 0 ix_reg long 0 iy_reg long 0 sp_reg long 0 pc_reg long 0 op_reg long 0 target_reg long 0 '--------------------------------------------------------------------------------------------------------- '--------------------------------------------------------------------------------------------------------- 'The I/O control block io_command long 0 io_port long 0 io_data long 0 '--------------------------------------------------------------------------------------------------------- '--------------------------------------------------------------------------------------------------------- fit '--------------------------------------------------------------------------------------------------------- '--------------------------------------------------------------------------------------------------------- dispatch_table {00} long fetch 'NOP {01} long get_immediate_word + (null_op << 9) + (put_bc << 18) 'LXI B * {02} long get_a + (null_op << 9) + (put_memory_bc << 18) 'STAX B * {03} long get_bc + (increment_word << 9) + (put_bc << 18) 'INX B * {04} long get_b + (increment_byte << 9) + (put_b << 18) 'INR B * {05} long get_b + (decrement_byte << 9) + (put_b << 18) 'DCR B * {06} long get_immediate_byte + (put_b << 9) 'MVI B * {07} long get_a + (alu_rlc << 9) + (put_a << 18) 'RLC * {08} long 0'EX {09} long get_bc + (double_add << 9) + (put_hl << 18) 'DAD B * {0A} long get_memory_bc + (null_op << 9) + (put_a << 18) 'LDAX B * {0B} long get_bc + (decrement_word << 9) + (put_bc << 18) 'DCX B * {0C} long get_c + (increment_byte << 9) + (put_c << 18) 'INR C * {0D} long get_c + (decrement_byte << 9) + (put_c << 18) 'DCR C * {0E} long get_immediate_byte + (put_c << 9) 'MVI C * {0F} long get_a + (alu_rrc << 9) + (put_a << 18) 'RRC * {10} long 0'NOP {11} long get_immediate_word + (null_op << 9) + (put_de << 18) 'LXI D * {12} long get_a + (null_op << 9) + (put_memory_de << 18) 'STAX D * {13} long get_de + (increment_word << 9) + (put_de << 18) 'INX D * {14} long get_d + (increment_byte << 9) + (put_d << 18) 'INR D * {15} long get_d + (decrement_byte << 9) + (put_d << 18) 'DCR D * {16} long get_immediate_byte + (put_d << 9) 'MVI D * {17} long get_a + (alu_ral << 9) + (put_a << 18) 'RAL * {18} long 0'EX {19} long get_de + (double_add << 9) + (put_hl << 18) 'DAD D * {1A} long get_memory_de + (null_op << 9) + (put_a << 18) 'LDAX D * {1B} long get_de + (decrement_word << 9) + (put_de << 18) 'DCX D * {1C} long get_e + (increment_byte << 9) + (put_e << 18) 'INR E * {1D} long get_e + (decrement_byte << 9) + (put_e << 18) 'DCR E * {1E} long get_immediate_byte + (put_e << 9) 'MVI E * {1F} long get_a + (alu_rar << 9) + (put_a << 18) 'RAR * {20} long 0'NOP {21} long get_immediate_word + (null_op << 9) + (put_hl << 18) 'LXI H * {22} long get_immediate_word + (store_hl_direct << 9) 'SHLD * {23} long get_hl + (increment_word << 9) + (put_hl << 18) 'INX H * {24} long get_h + (increment_byte << 9) + (put_h << 18) 'INR H * {25} long get_h + (decrement_byte << 9) + (put_h << 18) 'DCR H * {26} long get_immediate_byte + (put_h << 9) 'MVI H * {27} long get_a + (daa << 9) + (put_a << 18) 'DAA {28} long 0'EX {29} long get_hl + (double_add << 9) + (put_hl << 18) 'DAD H * {2A} long get_immediate_word + (load_hl_direct << 9) 'LHLD * {2B} long get_hl + (decrement_word << 9) + (put_hl << 18) 'DCX H * {2C} long get_l + (increment_byte << 9) + (put_l << 18) 'INR L * {2D} long get_l + (decrement_byte << 9) + (put_l << 18) 'DCR L * {2E} long get_immediate_byte + (put_l << 9) 'MVI L * {2F} long get_a + (complement_byte << 9) + (put_a << 18) 'CMA * {30} long 0'NOP {31} long get_immediate_word + (null_op << 9) + (put_sp << 18) 'LXI SP * {32} long get_immediate_word + (store_a_direct << 9) 'STA * {33} long get_sp + (increment_word << 9) + (put_sp << 18) 'INX SP * {34} long get_memory_hl + (increment_byte << 9) + (put_memory_hl << 18) 'INR M * {35} long get_memory_hl + (decrement_byte << 9) + (put_memory_hl << 18) 'DCR M * {36} long get_immediate_byte + (put_memory_hl << 9) 'MVI M * {37} long set_carry 'STC * {38} long 0'EX {39} long get_sp + (double_add << 9) + (put_hl << 18) 'DAD SP * {3A} long get_immediate_word + (load_a_direct << 9) 'LDA * {3B} long get_sp + (decrement_word << 9) + (put_sp << 18) 'DCX SP * {3C} long get_a + (increment_byte << 9) + (put_a << 18) 'INR A * {3D} long get_a + (decrement_byte << 9) + (put_a << 18) 'DCR A * {3E} long get_immediate_byte + (null_op << 9) + (put_a << 18) 'MVI A * {3F} long complement_carry 'CMC * {40} long fetch 'MOV B,B {41} long get_c + (put_b << 9) 'MOV B,C {42} long get_d + (put_b << 9) 'MOV B,D {43} long get_e + (put_b << 9) 'MOV B,E {44} long get_h + (put_b << 9) 'MOV B,H {45} long get_l + (put_b << 9) 'MOV B,L {46} long get_memory_hl + (put_b << 9) 'MOV B,M {47} long get_a + (put_b << 9) 'MOV B,A {48} long get_b + (put_c << 9) 'MOV C,B {49} long fetch 'MOV C,C {4A} long get_d + (put_c << 9) 'MOV C,D {4B} long get_e + (put_c << 9) 'MOV C,E {4C} long get_h + (put_c << 9) 'MOV C,H {4D} long get_l + (put_c << 9) 'MOV C,L {4E} long get_memory_hl + (put_c << 9) 'MOV C,M {4F} long get_a + (put_c << 9) 'MOV C,A {50} long get_b + (put_d << 9) 'MOV D,B {51} long get_c + (put_d << 9) 'MOV D,C {52} long fetch 'MOV D,D {53} long get_e + (put_d << 9) 'MOV D,E {54} long get_h + (put_d << 9) 'MOV D,H {55} long get_l + (put_d << 9) 'MOV D,L {56} long get_memory_hl + (put_d << 9) 'MOV D,M {57} long get_a + (put_d << 9) 'MOV D,A {58} long get_b + (put_e << 9) 'MOV E,B {59} long get_c + (put_e << 9) 'MOV E,C {5A} long get_d + (put_e << 9) 'MOV E,D {5B} long fetch 'MOV E,E {5C} long get_h + (put_e << 9) 'MOV E,H {5D} long get_l + (put_e << 9) 'MOV E,L {5E} long get_memory_hl + (put_e << 9) 'MOV E,M {5F} long get_a + (put_e << 9) 'MOV E,A {60} long get_b + (put_h << 9) 'MOV H,B {61} long get_c + (put_h << 9) 'MOV H,C {62} long get_d + (put_h << 9) 'MOV H,D {63} long get_e + (put_h << 9) 'MOV H,E {64} long fetch 'MOV H,H {65} long get_l + (put_h << 9) 'MOV H,L {66} long get_memory_hl + (put_h << 9) 'MOV H,M {67} long get_a + (put_h << 9) 'MOV H,A {68} long get_b + (put_l << 9) 'MOV L,B {69} long get_c + (put_l << 9) 'MOV L,C {6A} long get_d + (put_l << 9) 'MOV L,D {6B} long get_e + (put_l << 9) 'MOV L,E {6C} long get_h + (put_l << 9) 'MOV L,H {6D} long fetch 'MOV L,L {6E} long get_memory_hl + (put_l << 9) 'MOV L,M {6F} long get_a + (put_l << 9) 'MOV L,A {70} long get_b + (put_memory_hl << 9) 'MOV M,B {71} long get_c + (put_memory_hl << 9) 'MOV M,C {72} long get_d + (put_memory_hl << 9) 'MOV M,D {73} long get_e + (put_memory_hl << 9) 'MOV M,E {74} long get_h + (put_memory_hl << 9) 'MOV M,H {75} long get_l + (put_memory_hl << 9) 'MOV M,L {76} long 0 + (0 << 9) 'MOV M,M 'FIXME HALT {77} long get_a + (put_memory_hl << 9) 'MOV M,A {78} long get_b + (put_a << 9) 'MOV A,B {79} long get_c + (put_a << 9) 'MOV A,C {7A} long get_d + (put_a << 9) 'MOV A,D {7B} long get_e + (put_a << 9) 'MOV A,E {7C} long get_h + (put_a << 9) 'MOV A,H {7D} long get_l + (put_a << 9) 'MOV A,L {7E} long get_memory_hl + (put_a << 9) 'MOV A,M {7F} long fetch 'MOV A,A {80} long get_b + (alu_add << 9) + (put_a << 18) 'ADD B * {81} long get_c + (alu_add << 9) + (put_a << 18) 'ADD C * {82} long get_d + (alu_add << 9) + (put_a << 18) 'ADD D * {83} long get_e + (alu_add << 9) + (put_a << 18) 'ADD E * {84} long get_h + (alu_add << 9) + (put_a << 18) 'ADD H * {85} long get_l + (alu_add << 9) + (put_a << 18) 'ADD L * {86} long get_memory_hl + (alu_add << 9) + (put_a << 18) 'ADD M * {87} long get_a + (alu_add << 9) + (put_a << 18) 'ADD A * {88} long get_b + (alu_add_with_carry << 9) + (put_a << 18) 'ADC B * {89} long get_c + (alu_add_with_carry << 9) + (put_a << 18) 'ADC C * {8A} long get_d + (alu_add_with_carry << 9) + (put_a << 18) 'ADC D * {8B} long get_e + (alu_add_with_carry << 9) + (put_a << 18) 'ADC E * {8C} long get_h + (alu_add_with_carry << 9) + (put_a << 18) 'ADC H * {8D} long get_l + (alu_add_with_carry << 9) + (put_a << 18) 'ADC L * {8E} long get_memory_hl + (alu_add_with_carry << 9) + (put_a << 18) 'ADC M * {8F} long get_a + (alu_add_with_carry << 9) + (put_a << 18) 'ADC A * {90} long get_b + (alu_sub << 9) + (put_a << 18) 'SUB B * {91} long get_c + (alu_sub << 9) + (put_a << 18) 'SUB C * {92} long get_d + (alu_sub << 9) + (put_a << 18) 'SUB D * {93} long get_e + (alu_sub << 9) + (put_a << 18) 'SUB E * {94} long get_h + (alu_sub << 9) + (put_a << 18) 'SUB H * {95} long get_l + (alu_sub << 9) + (put_a << 18) 'SUB L * {96} long get_memory_hl + (alu_sub << 9) + (put_a << 18) 'SUB M * {97} long get_a + (alu_sub << 9) + (put_a << 18) 'SUB A * {98} long get_b + (alu_sub_with_borrow << 9) + (put_a << 18) 'SBB B * {99} long get_c + (alu_sub_with_borrow << 9) + (put_a << 18) 'SBB C * {9A} long get_d + (alu_sub_with_borrow << 9) + (put_a << 18) 'SBB D * {9B} long get_e + (alu_sub_with_borrow << 9) + (put_a << 18) 'SBB E * {9C} long get_h + (alu_sub_with_borrow << 9) + (put_a << 18) 'SBB H * {9D} long get_l + (alu_sub_with_borrow << 9) + (put_a << 18) 'SBB L * {9E} long get_memory_hl + (alu_sub_with_borrow << 9) + (put_a << 18) 'SBB M * {9F} long get_a + (alu_sub_with_borrow << 9) + (put_a << 18) 'SBB A * {A0} long get_b + (alu_and << 9) + (put_a << 18) 'AND B * {A1} long get_c + (alu_and << 9) + (put_a << 18) 'AND C * {A2} long get_d + (alu_and << 9) + (put_a << 18) 'AND D * {A3} long get_e + (alu_and << 9) + (put_a << 18) 'AND E * {A4} long get_h + (alu_and << 9) + (put_a << 18) 'AND H * {A5} long get_l + (alu_and << 9) + (put_a << 18) 'AND L * {A6} long get_memory_hl + (alu_and << 9) + (put_a << 18) 'AND M * {A7} long get_a + (alu_and << 9) + (put_a << 18) 'AND A * {A8} long get_b + (alu_xor << 9) + (put_a << 18) 'XRA B * {A9} long get_c + (alu_xor << 9) + (put_a << 18) 'XRA C * {AA} long get_d + (alu_xor << 9) + (put_a << 18) 'XRA D * {AB} long get_e + (alu_xor << 9) + (put_a << 18) 'XRA E * {AC} long get_h + (alu_xor << 9) + (put_a << 18) 'XRA H * {AD} long get_l + (alu_xor << 9) + (put_a << 18) 'XRA L * {AE} long get_memory_hl + (alu_xor << 9) + (put_a << 18) 'XRA M * {AF} long get_a + (alu_xor << 9) + (put_a << 18) 'XRA A * {B0} long get_b + (alu_or << 9) + (put_a << 18) 'ORA B * {B1} long get_c + (alu_or << 9) + (put_a << 18) 'ORA C * {B2} long get_d + (alu_or << 9) + (put_a << 18) 'ORA D * {B3} long get_e + (alu_or << 9) + (put_a << 18) 'ORA E * {B4} long get_h + (alu_or << 9) + (put_a << 18) 'ORA H * {B5} long get_l + (alu_or << 9) + (put_a << 18) 'ORA L * {B6} long get_memory_hl + (alu_or << 9) + (put_a << 18) 'ORA M * {B7} long get_a + (alu_or << 9) + (put_a << 18) 'ORA A * {B8} long get_b + (alu_sub << 9) + (fetch << 18) 'CMP B * FIXME cmp has no result !!! {B9} long get_c + (alu_sub << 9) + (fetch << 18) 'CMP C * {BA} long get_d + (alu_sub << 9) + (fetch << 18) 'CMP D * {BB} long get_e + (alu_sub << 9) + (fetch << 18) 'CMP E * {BC} long get_h + (alu_sub << 9) + (fetch << 18) 'CMP H * {BD} long get_l + (alu_sub << 9) + (fetch << 18) 'CMP L * {BE} long get_memory_hl + (alu_sub << 9) + (fetch << 18) 'CMP M * {BF} long get_a + (alu_sub << 9) + (fetch << 18) 'CMP A * { {11000000} long do_rnz {11000001} long do_pop_b {11000010} long do_jnz {11000011} long do_jmp {11000100} long do_cnz {11000101} long do_push_b {11000110} long do_adi {11000111} long do_rst_0 {11001000} long do_rz {11001001} long do_ret {11001010} long do_jz {11001011} long do_z80_CB 'Z80, CB Prefix {11001100} long do_cz {11001101} long do_call {11001110} long do_aci {11001111} long do_rst_1 } {C0} long test_flag_false + (return_conditional << 9) + (zero_bit << 18) 'RNZ {C1} long pop + (null_op << 9) + (put_bc << 18) 'POP B {C2} long test_flag_false + (jump_conditional << 9) + (zero_bit << 18) 'JNZ {C3} long jump_unconditional 'JMP * {C4} long test_flag_false + (call_conditional << 9) + (zero_bit << 18) 'CNZ {C5} long get_bc + (null_op << 9) + (push << 18) 'PUSH B {C6} long get_immediate_byte + (alu_add << 9) + (put_a << 18) 'ADI {C7} long restart + ((0 << 3) << 9) 'RST 0 {C8} long test_flag_true + (return_conditional << 9) + (zero_bit << 18) 'RZ {C9} long return_unconditional 'RET {CA} long test_flag_true + (jump_conditional << 9) + (zero_bit << 18) 'JZ {CB} long z80_CB 'Z80, CB Prefix {CC} long test_flag_true + (call_conditional << 9) + (zero_bit << 18) 'CZ {CD} long call_unconditional 'CALL {CE} long get_immediate_byte + (alu_add_with_carry << 9) + (put_a << 18) 'ACI {CF} long restart + ((1 << 3) << 9) 'RST 1 { {11010000} long do_rnc {11010001} long do_pop_d {11010010} long do_jnc {11010011} long do_out {11010100} long do_cnc {11010101} long do_push_d {11010110} long do_sui {11010111} long do_rst_2 {11011000} long do_rc {11011001} long do_z80_exx 'Z80, D9, BC/DE/HL <-> BC'/DE'/HL' {11011010} long do_jc {11011011} long do_in {11011100} long do_cc {11011101} long do_z80_DD 'Z80 DD Prefix {11011110} long do_sbi {11011111} long do_rst_3 } {D0} long test_flag_false + (return_conditional << 9) + (carry_bit << 18) 'RNC {D1} long pop + (null_op << 9) + (put_bc << 18) 'POP D {D2} long test_flag_false + (jump_conditional << 9) + (carry_bit << 18) 'JNC {D3} long out {D4} long test_flag_false + (call_conditional << 9) + (carry_bit << 18) 'CNC {D5} long get_de + (null_op << 9) + (push << 18) 'PUSH D {D6} long get_immediate_byte + (alu_sub << 9) + (put_a << 18) 'SUI {D7} long restart + ((2 << 3) << 9) 'RST 2 {D8} long test_flag_true + (return_conditional << 9) + (carry_bit << 18) 'RC {D9} long z80_exx 'Z80, D9, BC/DE/HL <-> BC'/DE'/HL' {DA} long test_flag_true + (jump_conditional << 9) + (carry_bit << 18) 'JC {DB} long in {DC} long test_flag_true + (call_conditional << 9) + (carry_bit << 18) 'CC {DD} long z80_DD 'Z80 DD Prefix {DE} long get_immediate_byte + (alu_sub_with_borrow << 9) + (put_a << 18) 'SBI {DF} long restart + ((3 << 3) << 9) 'RST 3 { {11100000} long do_rpo {11100001} long do_pop_h {11100010} long do_jpo {11100011} long do_xthl {11100100} long do_cpo {11100101} long do_push_h {11100110} long do_ani {11100111} long do_rst_4 {11101000} long do_rpe {11101001} long do_pchl {11101010} long do_jpe {11101011} long do_xchg {11101100} long do_cpe {11101101} long do_z80_ED 'Z80 ED Prefix {11101110} long do_xri {11101111} long do_rst_5 } {E0} long test_flag_false + (return_conditional << 9) + (parity_bit << 18) 'RPO {E1} long pop + (null_op << 9) + (put_bc << 18) 'POP H {E2} long test_flag_false + (jump_conditional << 9) + (parity_bit << 18) 'JPO {E3} long 0 {E4} long test_flag_false + (call_conditional << 9) + (parity_bit << 18) 'CPO {E5} long get_hl + (null_op << 9) + (push << 18) 'PUSH H {E6} long get_immediate_byte + (alu_and << 9) + (put_a << 18) 'ANI {E7} long restart + ((4 << 3) << 9) 'RST 4 {E8} long test_flag_true + (return_conditional << 9) + (parity_bit << 18) 'RPE {E9} long 0 {EA} long test_flag_true + (jump_conditional << 9) + (parity_bit << 18) 'JPE {EB} long 0 {EC} long test_flag_true + (call_conditional << 9) + (parity_bit << 18) 'CPE {ED} long z80_ED 'Z80 ED Prefix {EE} long get_immediate_byte + (alu_xor << 9) + (put_a << 18) 'XRI {EF} long restart + ((5 << 3) << 9) 'RST 5 { {11110000} long do_rp {11110001} long do_pop_af {11110010} long do_jp {11110011} long do_di {11110100} long do_cp {11110101} long do_push_af {11110110} long do_ori {11110111} long do_rst_6 {11111000} long do_rm {11111001} long do_sphl {11111010} long do_jm {11111011} long do_ei {11111100} long do_cm {11111101} long do_z80_FD 'Z80 FD Prefix {11111110} long do_cpi {11111111} long do_rst_7 } {F0} long test_flag_false + (return_conditional << 9) + (sign_bit << 18) 'RP {F1} long pop + (null_op << 9) + (put_bc << 18) 'POP AF {F2} long test_flag_false + (jump_conditional << 9) + (sign_bit << 18) 'JP {F3} long 0 {F4} long test_flag_false + (call_conditional << 9) + (sign_bit << 18) 'CP {F5} long get_af + (null_op << 9) + (push << 18) 'PUSH AF {F6} long get_immediate_byte + (alu_or << 9) + (put_a << 18) 'ORI {F7} long restart + ((6 << 3) << 9) 'RST 6 {F8} long test_flag_true + (return_conditional << 9) + (sign_bit << 18) 'RM {F9} long 0 {FA} long test_flag_true + (jump_conditional << 9) + (sign_bit << 18) 'JM {FB} long 0 {FC} long test_flag_true + (call_conditional << 9) + (sign_bit << 18) 'CM {FD} long z80_FD 'Z80 FD Prefix {FE} long get_immediate_byte + (alu_sub << 9) + (0 << 18) 'CPI FIXME cpi has no result. {FF} long restart + ((7 << 3) << 9) 'RST 7 '--------------------------------------------------------------------------------------------------------- '--------------------------------------------------------------------------------------------------------- dispatch_table_z80_cb_prefix {00} long get_b + (alu_rlc << 9) + (put_b << 18) 'RLC B CB00 --- {00} long get_c + (alu_rlc << 9) + (put_c << 18) 'RLC C CB01 --- {00} long get_d + (alu_rlc << 9) + (put_d << 18) 'RLC D CB02 --- {00} long get_e + (alu_rlc << 9) + (put_e << 18) 'RLC E CB03 --- {00} long get_h + (alu_rlc << 9) + (put_h << 18) 'RLC H CB04 --- {00} long get_l + (alu_rlc << 9) + (put_l << 18) 'RLC L CB05 --- {00} long get_memory_hl + (alu_rlc << 9) + (put_memory_hl << 18) 'RLC (HL) CB06 --- {00} long get_a + (alu_rlc << 9) + (put_a << 18) 'RLC A CB07 --- {00} long get_b + (alu_rrc << 9) + (put_b << 18) 'RRC B CB08 --- {00} long get_c + (alu_rrc << 9) + (put_c << 18) 'RRC C CB09 --- {00} long get_d + (alu_rrc << 9) + (put_d << 18) 'RRC D CB0A --- {00} long get_e + (alu_rrc << 9) + (put_e << 18) 'RRC E CB0B --- {00} long get_h + (alu_rrc << 9) + (put_h << 18) 'RRC H CB0C --- {00} long get_l + (alu_rrc << 9) + (put_l << 18) 'RRC L CB0D --- {00} long get_memory_hl + (alu_rrc << 9) + (put_memory_hl << 18) 'RRC (HL) CB0E --- {00} long get_a + (alu_rrc << 9) + (put_a << 18) 'RRC A CB0F --- {00} long get_b + (alu_ral << 9) + (put_b << 18) 'RL B CB10 --- {00} long get_c + (alu_ral << 9) + (put_c << 18) 'RL C CB11 --- {00} long get_d + (alu_ral << 9) + (put_d << 18) 'RL D CB12 --- {00} long get_e + (alu_ral << 9) + (put_e << 18) 'RL E CB13 --- {00} long get_h + (alu_ral << 9) + (put_h << 18) 'RL H CB14 --- {00} long get_l + (alu_ral << 9) + (put_l << 18) 'RL L CB15 --- {00} long get_memory_hl + (alu_ral << 9) + (put_memory_hl << 18) 'RL (HL) CB16 --- {00} long get_a + (alu_ral << 9) + (put_a << 18) 'RL A CB17 --- {00} long get_b + (alu_rar << 9) + (put_b << 18) 'RR B CB18 --- {00} long get_c + (alu_rar << 9) + (put_c << 18) 'RR C CB19 --- {00} long get_d + (alu_rar << 9) + (put_d << 18) 'RR D CB1A --- {00} long get_e + (alu_rar << 9) + (put_e << 18) 'RR E CB1B --- {00} long get_h + (alu_rar << 9) + (put_h << 18) 'RR H CB1C --- {00} long get_l + (alu_rar << 9) + (put_l << 18) 'RR L CB1D --- {00} long get_memory_hl + (alu_rar << 9) + (put_memory_hl << 18) 'RR (HL) CB1E --- {00} long get_a + (alu_rar << 9) + (put_a << 18) 'RR A CB1F --- {00} long get_b + (alu_sla << 9) + (put_b << 18) 'SLA B CB20 --- {00} long get_c + (alu_sla << 9) + (put_c << 18) 'SLA C CB21 --- {00} long get_d + (alu_sla << 9) + (put_d << 18) 'SLA D CB22 --- {00} long get_e + (alu_sla << 9) + (put_e << 18) 'SLA E CB23 --- {00} long get_h + (alu_sla << 9) + (put_h << 18) 'SLA H CB24 --- {00} long get_l + (alu_sla << 9) + (put_l << 18) 'SLA L CB25 --- {00} long get_memory_hl + (alu_sla << 9) + (put_memory_hl << 18) 'SLA (HL) CB26 --- {00} long get_a + (alu_sla << 9) + (put_a << 18) 'SLA A CB27 --- {00} long get_b + (alu_sra << 9) + (put_b << 18) 'SRA B CB28 --- {00} long get_c + (alu_sra << 9) + (put_c << 18) 'SRA C CB29 --- {00} long get_d + (alu_sra << 9) + (put_d << 18) 'SRA D CB2A --- {00} long get_e + (alu_sra << 9) + (put_e << 18) 'SRA E CB2B --- {00} long get_h + (alu_sra << 9) + (put_h << 18) 'SRA H CB2C --- {00} long get_l + (alu_sra << 9) + (put_l << 18) 'SRA L CB2D --- {00} long get_memory_hl + (alu_sra << 9) + (put_memory_hl << 18) 'SRA (HL) CB2E --- {00} long get_a + (alu_sra << 9) + (put_a << 18) 'SRA A CB2F --- {30} {31} {32} {33} {34} {35} {36} {37} {00} long get_b + (alu_srl << 9) + (put_b << 18) 'SRL B CB38 --- {00} long get_c + (alu_srl << 9) + (put_c << 18) 'SRL C CB39 --- {00} long get_d + (alu_srl << 9) + (put_d << 18) 'SRL D CB3A --- {00} long get_e + (alu_srl << 9) + (put_e << 18) 'SRL E CB3B --- {00} long get_h + (alu_srl << 9) + (put_h << 18) 'SRL H CB3C --- {00} long get_l + (alu_srl << 9) + (put_l << 18) 'SRL L CB3D --- {00} long get_memory_hl + (alu_srl << 9) + (put_memory_hl << 18) 'SRL (HL) CB3E --- {00} long get_a + (alu_srl << 9) + (put_a << 18) 'SRL A CB3F --- {00} long get_b + (alu_bit << 9) + (put_b << 18) + (0 << 27) 'BIT 0,B CB40 Z flag <- NOT 0b {00} long get_c + (alu_bit << 9) + (put_c << 18) + (0 << 27) 'BIT 0,C CB41 Z flag <- NOT 0b {00} long get_d + (alu_bit << 9) + (put_d << 18) + (0 << 27) 'BIT 0,D CB42 Z flag <- NOT 0b {00} long get_e + (alu_bit << 9) + (put_e << 18) + (0 << 27) 'BIT 0,E CB43 Z flag <- NOT 0b {00} long get_h + (alu_bit << 9) + (put_h << 18) + (0 << 27) 'BIT 0,H CB44 Z flag <- NOT 0b {00} long get_l + (alu_bit << 9) + (put_l << 18) + (0 << 27) 'BIT 0,L CB45 Z flag <- NOT 0b {00} long get_m + (alu_bit << 9) + (put_m << 18) + (0 << 27) 'BIT 0,(HL) CB46 Z flag <- NOT 0b {00} long get_a + (alu_bit << 9) + (put_a << 18) + (0 << 27) 'BIT 0,A CB47 Z flag <- NOT 0b {00} long get_b + (alu_bit << 9) + (put_b << 18) + (1 << 27) 'BIT 1,B CB48 Z flag <- NOT 1b {00} long get_c + (alu_bit << 9) + (put_c << 18) + (1 << 27) 'BIT 1,C CB49 Z flag <- NOT 1b {00} long get_d + (alu_bit << 9) + (put_d << 18) + (1 << 27) 'BIT 1,D CB4A Z flag <- NOT 1b {00} long get_e + (alu_bit << 9) + (put_e << 18) + (1 << 27) 'BIT 1,E CB4B Z flag <- NOT 1b {00} long get_h + (alu_bit << 9) + (put_h << 18) + (1 << 27) 'BIT 1,H CB4C Z flag <- NOT 1b {00} long get_l + (alu_bit << 9) + (put_l << 18) + (1 << 27) 'BIT 1,L CB4D Z flag <- NOT 1b {00} long get_m + (alu_bit << 9) + (put_m << 18) + (1 << 27) 'BIT 1,(HL) CB4E Z flag <- NOT 1b {00} long get_a + (alu_bit << 9) + (put_a << 18) + (1 << 27) 'BIT 1,A CB4F Z flag <- NOT 1b {00} long get_b + (alu_bit << 9) + (put_b << 18) + (2 << 27) 'BIT 2,B CB50 Z flag <- NOT 2b {00} long get_c + (alu_bit << 9) + (put_c << 18) + (2 << 27) 'BIT 2,C CB51 Z flag <- NOT 2b {00} long get_d + (alu_bit << 9) + (put_d << 18) + (2 << 27) 'BIT 2,D CB52 Z flag <- NOT 2b {00} long get_e + (alu_bit << 9) + (put_e << 18) + (2 << 27) 'BIT 2,E CB53 Z flag <- NOT 2b {00} long get_h + (alu_bit << 9) + (put_h << 18) + (2 << 27) 'BIT 2,H CB54 Z flag <- NOT 2b {00} long get_l + (alu_bit << 9) + (put_l << 18) + (2 << 27) 'BIT 2,L CB55 Z flag <- NOT 2b {00} long get_m + (alu_bit << 9) + (put_m << 18) + (2 << 27) 'BIT 2,(HL) CB56 Z flag <- NOT 2b {00} long get_a + (alu_bit << 9) + (put_a << 18) + (2 << 27) 'BIT 2,A CB57 Z flag <- NOT 2b {00} long get_b + (alu_bit << 9) + (put_b << 18) + (3 << 27) 'BIT 3,B CB58 Z flag <- NOT 3b {00} long get_c + (alu_bit << 9) + (put_c << 18) + (3 << 27) 'BIT 3,C CB59 Z flag <- NOT 3b {00} long get_d + (alu_bit << 9) + (put_d << 18) + (3 << 27) 'BIT 3,D CB5A Z flag <- NOT 3b {00} long get_e + (alu_bit << 9) + (put_e << 18) + (3 << 27) 'BIT 3,E CB5B Z flag <- NOT 3b {00} long get_h + (alu_bit << 9) + (put_h << 18) + (3 << 27) 'BIT 3,H CB5C Z flag <- NOT 3b {00} long get_l + (alu_bit << 9) + (put_l << 18) + (3 << 27) 'BIT 3,L CB5D Z flag <- NOT 3b {00} long get_m + (alu_bit << 9) + (put_m << 18) + (3 << 27) 'BIT 3,(HL) CB5E Z flag <- NOT 3b {00} long get_a + (alu_bit << 9) + (put_a << 18) + (3 << 27) 'BIT 3,A CB5F Z flag <- NOT 3b {00} long get_b + (alu_bit << 9) + (put_b << 18) + (4 << 27) 'BIT 4,B CB60 Z flag <- NOT 4b {00} long get_c + (alu_bit << 9) + (put_c << 18) + (4 << 27) 'BIT 4,C CB61 Z flag <- NOT 4b {00} long get_d + (alu_bit << 9) + (put_d << 18) + (4 << 27) 'BIT 4,D CB62 Z flag <- NOT 4b {00} long get_e + (alu_bit << 9) + (put_e << 18) + (4 << 27) 'BIT 4,E CB63 Z flag <- NOT 4b {00} long get_h + (alu_bit << 9) + (put_h << 18) + (4 << 27) 'BIT 4,H CB64 Z flag <- NOT 4b {00} long get_l + (alu_bit << 9) + (put_l << 18) + (4 << 27) 'BIT 4,L CB65 Z flag <- NOT 4b {00} long get_m + (alu_bit << 9) + (put_m << 18) + (4 << 27) 'BIT 4,(HL) CB66 Z flag <- NOT 4b {00} long get_a + (alu_bit << 9) + (put_a << 18) + (4 << 27) 'BIT 4,A CB67 Z flag <- NOT 4b {00} long get_b + (alu_bit << 9) + (put_b << 18) + (5 << 27) 'BIT 5,B CB68 Z flag <- NOT 5b {00} long get_c + (alu_bit << 9) + (put_c << 18) + (5 << 27) 'BIT 5,C CB69 Z flag <- NOT 5b {00} long get_d + (alu_bit << 9) + (put_d << 18) + (5 << 27) 'BIT 5,D CB6A Z flag <- NOT 5b {00} long get_e + (alu_bit << 9) + (put_e << 18) + (5 << 27) 'BIT 5,E CB6B Z flag <- NOT 5b {00} long get_h + (alu_bit << 9) + (put_h << 18) + (5 << 27) 'BIT 5,H CB6C Z flag <- NOT 5b {00} long get_l + (alu_bit << 9) + (put_l << 18) + (5 << 27) 'BIT 5,L CB6D Z flag <- NOT 5b {00} long get_m + (alu_bit << 9) + (put_m << 18) + (5 << 27) 'BIT 5,(HL) CB6E Z flag <- NOT 5b {00} long get_a + (alu_bit << 9) + (put_a << 18) + (5 << 27) 'BIT 5,A CB6F Z flag <- NOT 5b {00} long get_b + (alu_bit << 9) + (put_b << 18) + (6 << 27) 'BIT 6,B CB70 Z flag <- NOT 6b {00} long get_c + (alu_bit << 9) + (put_c << 18) + (6 << 27) 'BIT 6,C CB71 Z flag <- NOT 6b {00} long get_d + (alu_bit << 9) + (put_d << 18) + (6 << 27) 'BIT 6,D CB72 Z flag <- NOT 6b {00} long get_e + (alu_bit << 9) + (put_e << 18) + (6 << 27) 'BIT 6,E CB73 Z flag <- NOT 6b {00} long get_h + (alu_bit << 9) + (put_h << 18) + (6 << 27) 'BIT 6,H CB74 Z flag <- NOT 6b {00} long get_l + (alu_bit << 9) + (put_l << 18) + (6 << 27) 'BIT 6,L CB75 Z flag <- NOT 6b {00} long get_m + (alu_bit << 9) + (put_m << 18) + (6 << 27) 'BIT 6,(HL) CB76 Z flag <- NOT 6b {00} long get_a + (alu_bit << 9) + (put_a << 18) + (6 << 27) 'BIT 6,A CB77 Z flag <- NOT 6b {00} long get_b + (alu_bit << 9) + (put_b << 18) + (7 << 27) 'BIT 7,B CB78 Z flag <- NOT 7b {00} long get_c + (alu_bit << 9) + (put_c << 18) + (7 << 27) 'BIT 7,C CB79 Z flag <- NOT 7b {00} long get_d + (alu_bit << 9) + (put_d << 18) + (7 << 27) 'BIT 7,D CB7A Z flag <- NOT 7b {00} long get_e + (alu_bit << 9) + (put_e << 18) + (7 << 27) 'BIT 7,E CB7B Z flag <- NOT 7b {00} long get_h + (alu_bit << 9) + (put_h << 18) + (7 << 27) 'BIT 7,H CB7C Z flag <- NOT 7b {00} long get_l + (alu_bit << 9) + (put_l << 18) + (7 << 27) 'BIT 7,L CB7D Z flag <- NOT 7b {00} long get_m + (alu_bit << 9) + (put_m << 18) + (7 << 27) 'BIT 7,(HL) CB7E Z flag <- NOT 7b {00} long get_a + (alu_bit << 9) + (put_a << 18) + (7 << 27) 'BIT 7,A CB7F Z flag <- NOT 7b {00} long get_b + (alu_res << 9) + (put_b << 18) + (0 << 27) 'RES 0,B CB80 0b <- 0 {00} long get_c + (alu_res << 9) + (put_c << 18) + (0 << 27) 'RES 0,C CB81 0b <- 0 {00} long get_d + (alu_res << 9) + (put_d << 18) + (0 << 27) 'RES 0,D CB82 0b <- 0 {00} long get_e + (alu_res << 9) + (put_e << 18) + (0 << 27) 'RES 0,E CB83 0b <- 0 {00} long get_h + (alu_res << 9) + (put_h << 18) + (0 << 27) 'RES 0,H CB84 0b <- 0 {00} long get_l + (alu_res << 9) + (put_l << 18) + (0 << 27) 'RES 0,L CB85 0b <- 0 {00} long get_m + (alu_res << 9) + (put_m << 18) + (0 << 27) 'RES 0,(HL) CB86 0b <- 0 {00} long get_a + (alu_res << 9) + (put_a << 18) + (0 << 27) 'RES 0,A CB87 0b <- 0 {00} long get_b + (alu_res << 9) + (put_b << 18) + (1 << 27) 'RES 1,B CB88 1b <- 0 {00} long get_c + (alu_res << 9) + (put_c << 18) + (1 << 27) 'RES 1,C CB89 1b <- 0 {00} long get_d + (alu_res << 9) + (put_d << 18) + (1 << 27) 'RES 1,D CB8A 1b <- 0 {00} long get_e + (alu_res << 9) + (put_e << 18) + (1 << 27) 'RES 1,E CB8B 1b <- 0 {00} long get_h + (alu_res << 9) + (put_h << 18) + (1 << 27) 'RES 1,H CB8C 1b <- 0 {00} long get_l + (alu_res << 9) + (put_l << 18) + (1 << 27) 'RES 1,L CB8D 1b <- 0 {00} long get_m + (alu_res << 9) + (put_m << 18) + (1 << 27) 'RES 1,(HL) CB8E 1b <- 0 {00} long get_a + (alu_res << 9) + (put_a << 18) + (1 << 27) 'RES 1,A CB8F 1b <- 0 {00} long get_b + (alu_res << 9) + (put_b << 18) + (2 << 27) 'RES 2,B CB90 2b <- 0 {00} long get_c + (alu_res << 9) + (put_c << 18) + (2 << 27) 'RES 2,C CB91 2b <- 0 {00} long get_d + (alu_res << 9) + (put_d << 18) + (2 << 27) 'RES 2,D CB92 2b <- 0 {00} long get_e + (alu_res << 9) + (put_e << 18) + (2 << 27) 'RES 2,E CB93 2b <- 0 {00} long get_h + (alu_res << 9) + (put_h << 18) + (2 << 27) 'RES 2,H CB94 2b <- 0 {00} long get_l + (alu_res << 9) + (put_l << 18) + (2 << 27) 'RES 2,L CB95 2b <- 0 {00} long get_m + (alu_res << 9) + (put_m << 18) + (2 << 27) 'RES 2,(HL) CB96 2b <- 0 {00} long get_a + (alu_res << 9) + (put_a << 18) + (2 << 27) 'RES 2,A CB97 2b <- 0 {00} long get_b + (alu_res << 9) + (put_b << 18) + (3 << 27) 'RES 3,B CB98 3b <- 0 {00} long get_c + (alu_res << 9) + (put_c << 18) + (3 << 27) 'RES 3,C CB99 3b <- 0 {00} long get_d + (alu_res << 9) + (put_d << 18) + (3 << 27) 'RES 3,D CB9A 3b <- 0 {00} long get_e + (alu_res << 9) + (put_e << 18) + (3 << 27) 'RES 3,E CB9B 3b <- 0 {00} long get_h + (alu_res << 9) + (put_h << 18) + (3 << 27) 'RES 3,H CB9C 3b <- 0 {00} long get_l + (alu_res << 9) + (put_l << 18) + (3 << 27) 'RES 3,L CB9D 3b <- 0 {00} long get_m + (alu_res << 9) + (put_m << 18) + (3 << 27) 'RES 3,(HL) CB9E 3b <- 0 {00} long get_a + (alu_res << 9) + (put_a << 18) + (3 << 27) 'RES 3,A CB9F 3b <- 0 {00} long get_b + (alu_res << 9) + (put_b << 18) + (4 << 27) 'RES 4,B CBA0 4b <- 0 {00} long get_c + (alu_res << 9) + (put_c << 18) + (4 << 27) 'RES 4,C CBA1 4b <- 0 {00} long get_d + (alu_res << 9) + (put_d << 18) + (4 << 27) 'RES 4,D CBA2 4b <- 0 {00} long get_e + (alu_res << 9) + (put_e << 18) + (4 << 27) 'RES 4,E CBA3 4b <- 0 {00} long get_h + (alu_res << 9) + (put_h << 18) + (4 << 27) 'RES 4,H CBA4 4b <- 0 {00} long get_l + (alu_res << 9) + (put_l << 18) + (4 << 27) 'RES 4,L CBA5 4b <- 0 {00} long get_m + (alu_res << 9) + (put_m << 18) + (4 << 27) 'RES 4,(HL) CBA6 4b <- 0 {00} long get_a + (alu_res << 9) + (put_a << 18) + (4 << 27) 'RES 4,A CBA7 4b <- 0 {00} long get_b + (alu_res << 9) + (put_b << 18) + (5 << 27) 'RES 5,B CBA8 5b <- 0 {00} long get_c + (alu_res << 9) + (put_c << 18) + (5 << 27) 'RES 5,C CBA9 5b <- 0 {00} long get_d + (alu_res << 9) + (put_d << 18) + (5 << 27) 'RES 5,D CBAA 5b <- 0 {00} long get_e + (alu_res << 9) + (put_e << 18) + (5 << 27) 'RES 5,E CBAB 5b <- 0 {00} long get_h + (alu_res << 9) + (put_h << 18) + (5 << 27) 'RES 5,H CBAC 5b <- 0 {00} long get_l + (alu_res << 9) + (put_l << 18) + (5 << 27) 'RES 5,L CBAD 5b <- 0 {00} long get_m + (alu_res << 9) + (put_m << 18) + (5 << 27) 'RES 5,(HL) CBAE 5b <- 0 {00} long get_a + (alu_res << 9) + (put_a << 18) + (5 << 27) 'RES 5,A CBAF 5b <- 0 {00} long get_b + (alu_res << 9) + (put_b << 18) + (6 << 27) 'RES 6,B CBB0 6b <- 0 {00} long get_c + (alu_res << 9) + (put_c << 18) + (6 << 27) 'RES 6,C CBB1 6b <- 0 {00} long get_d + (alu_res << 9) + (put_d << 18) + (6 << 27) 'RES 6,D CBB2 6b <- 0 {00} long get_e + (alu_res << 9) + (put_e << 18) + (6 << 27) 'RES 6,E CBB3 6b <- 0 {00} long get_h + (alu_res << 9) + (put_h << 18) + (6 << 27) 'RES 6,H CBB4 6b <- 0 {00} long get_l + (alu_res << 9) + (put_l << 18) + (6 << 27) 'RES 6,L CBB5 6b <- 0 {00} long get_m + (alu_res << 9) + (put_m << 18) + (6 << 27) 'RES 6,(HL) CBB6 6b <- 0 {00} long get_a + (alu_res << 9) + (put_a << 18) + (6 << 27) 'RES 6,A CBB7 6b <- 0 {00} long get_b + (alu_res << 9) + (put_b << 18) + (7 << 27) 'RES 7,B CBB8 7b <- 0 {00} long get_c + (alu_res << 9) + (put_c << 18) + (7 << 27) 'RES 7,C CBB9 7b <- 0 {00} long get_d + (alu_res << 9) + (put_d << 18) + (7 << 27) 'RES 7,D CBBA 7b <- 0 {00} long get_e + (alu_res << 9) + (put_e << 18) + (7 << 27) 'RES 7,E CBBB 7b <- 0 {00} long get_h + (alu_res << 9) + (put_h << 18) + (7 << 27) 'RES 7,H CBBC 7b <- 0 {00} long get_l + (alu_res << 9) + (put_l << 18) + (7 << 27) 'RES 7,L CBBD 7b <- 0 {00} long get_m + (alu_res << 9) + (put_m << 18) + (7 << 27) 'RES 7,(HL) CBBE 7b <- 0 {00} long get_a + (alu_res << 9) + (put_a << 18) + (7 << 27) 'RES 7,A CBBF 7b <- 0 {00} long get_b + (alu_set << 9) + (put_b << 18) + (0 << 27) 'SET 0,B CBC0 0b <- 1 {00} long get_c + (alu_set << 9) + (put_c << 18) + (0 << 27) 'SET 0,C CBC1 0b <- 1 {00} long get_d + (alu_set << 9) + (put_d << 18) + (0 << 27) 'SET 0,D CBC2 0b <- 1 {00} long get_e + (alu_set << 9) + (put_e << 18) + (0 << 27) 'SET 0,E CBC3 0b <- 1 {00} long get_h + (alu_set << 9) + (put_h << 18) + (0 << 27) 'SET 0,H CBC4 0b <- 1 {00} long get_l + (alu_set << 9) + (put_l << 18) + (0 << 27) 'SET 0,L CBC5 0b <- 1 {00} long get_m + (alu_set << 9) + (put_m << 18) + (0 << 27) 'SET 0,(HL) CBC6 0b <- 1 {00} long get_a + (alu_set << 9) + (put_a << 18) + (0 << 27) 'SET 0,A CBC7 0b <- 1 {00} long get_b + (alu_set << 9) + (put_b << 18) + (1 << 27) 'SET 1,B CBC8 1b <- 1 {00} long get_c + (alu_set << 9) + (put_c << 18) + (1 << 27) 'SET 1,C CBC9 1b <- 1 {00} long get_d + (alu_set << 9) + (put_d << 18) + (1 << 27) 'SET 1,D CBCA 1b <- 1 {00} long get_e + (alu_set << 9) + (put_e << 18) + (1 << 27) 'SET 1,E CBCB 1b <- 1 {00} long get_h + (alu_set << 9) + (put_h << 18) + (1 << 27) 'SET 1,H CBCC 1b <- 1 {00} long get_l + (alu_set << 9) + (put_l << 18) + (1 << 27) 'SET 1,L CBCD 1b <- 1 {00} long get_m + (alu_set << 9) + (put_m << 18) + (1 << 27) 'SET 1,(HL) CBCE 1b <- 1 {00} long get_a + (alu_set << 9) + (put_a << 18) + (1 << 27) 'SET 1,A CBCF 1b <- 1 {00} long get_b + (alu_set << 9) + (put_b << 18) + (2 << 27) 'SET 2,B CBD0 2b <- 1 {00} long get_c + (alu_set << 9) + (put_c << 18) + (2 << 27) 'SET 2,C CBD1 2b <- 1 {00} long get_d + (alu_set << 9) + (put_d << 18) + (2 << 27) 'SET 2,D CBD2 2b <- 1 {00} long get_e + (alu_set << 9) + (put_e << 18) + (2 << 27) 'SET 2,E CBD3 2b <- 1 {00} long get_h + (alu_set << 9) + (put_h << 18) + (2 << 27) 'SET 2,H CBD4 2b <- 1 {00} long get_l + (alu_set << 9) + (put_l << 18) + (2 << 27) 'SET 2,L CBD5 2b <- 1 {00} long get_m + (alu_set << 9) + (put_m << 18) + (2 << 27) 'SET 2,(HL) CBD6 2b <- 1 {00} long get_a + (alu_set << 9) + (put_a << 18) + (2 << 27) 'SET 2,A CBD7 2b <- 1 {00} long get_b + (alu_set << 9) + (put_b << 18) + (3 << 27) 'SET 3,B CBD8 3b <- 1 {00} long get_c + (alu_set << 9) + (put_c << 18) + (3 << 27) 'SET 3,C CBD9 3b <- 1 {00} long get_d + (alu_set << 9) + (put_d << 18) + (3 << 27) 'SET 3,D CBDA 3b <- 1 {00} long get_e + (alu_set << 9) + (put_e << 18) + (3 << 27) 'SET 3,E CBDB 3b <- 1 {00} long get_h + (alu_set << 9) + (put_h << 18) + (3 << 27) 'SET 3,H CBDC 3b <- 1 {00} long get_l + (alu_set << 9) + (put_l << 18) + (3 << 27) 'SET 3,L CBDD 3b <- 1 {00} long get_m + (alu_set << 9) + (put_m << 18) + (3 << 27) 'SET 3,(HL) CBDE 3b <- 1 {00} long get_a + (alu_set << 9) + (put_a << 18) + (3 << 27) 'SET 3,A CBDF 3b <- 1 {00} long get_b + (alu_set << 9) + (put_b << 18) + (4 << 27) 'SET 4,B CBE0 4b <- 1 {00} long get_c + (alu_set << 9) + (put_c << 18) + (4 << 27) 'SET 4,C CBE1 4b <- 1 {00} long get_d + (alu_set << 9) + (put_d << 18) + (4 << 27) 'SET 4,D CBE2 4b <- 1 {00} long get_e + (alu_set << 9) + (put_e << 18) + (4 << 27) 'SET 4,E CBE3 4b <- 1 {00} long get_h + (alu_set << 9) + (put_h << 18) + (4 << 27) 'SET 4,H CBE4 4b <- 1 {00} long get_l + (alu_set << 9) + (put_l << 18) + (4 << 27) 'SET 4,L CBE5 4b <- 1 {00} long get_m + (alu_set << 9) + (put_m << 18) + (4 << 27) 'SET 4,(HL) CBE6 4b <- 1 {00} long get_a + (alu_set << 9) + (put_a << 18) + (4 << 27) 'SET 4,A CBE7 4b <- 1 {00} long get_b + (alu_set << 9) + (put_b << 18) + (5 << 27) 'SET 5,B CBE8 5b <- 1 {00} long get_c + (alu_set << 9) + (put_c << 18) + (5 << 27) 'SET 5,C CBE9 5b <- 1 {00} long get_d + (alu_set << 9) + (put_d << 18) + (5 << 27) 'SET 5,D CBEA 5b <- 1 {00} long get_e + (alu_set << 9) + (put_e << 18) + (5 << 27) 'SET 5,E CBEB 5b <- 1 {00} long get_h + (alu_set << 9) + (put_h << 18) + (5 << 27) 'SET 5,H CBEC 5b <- 1 {00} long get_l + (alu_set << 9) + (put_l << 18) + (5 << 27) 'SET 5,L CBED 5b <- 1 {00} long get_m + (alu_set << 9) + (put_m << 18) + (5 << 27) 'SET 5,(HL) CBEE 5b <- 1 {00} long get_a + (alu_set << 9) + (put_a << 18) + (5 << 27) 'SET 5,A CBEF 5b <- 1 {00} long get_b + (alu_set << 9) + (put_b << 18) + (6 << 27) 'SET 6,B CBF0 6b <- 1 {00} long get_c + (alu_set << 9) + (put_c << 18) + (6 << 27) 'SET 6,C CBF1 6b <- 1 {00} long get_d + (alu_set << 9) + (put_d << 18) + (6 << 27) 'SET 6,D CBF2 6b <- 1 {00} long get_e + (alu_set << 9) + (put_e << 18) + (6 << 27) 'SET 6,E CBF3 6b <- 1 {00} long get_h + (alu_set << 9) + (put_h << 18) + (6 << 27) 'SET 6,H CBF4 6b <- 1 {00} long get_l + (alu_set << 9) + (put_l << 18) + (6 << 27) 'SET 6,L CBF5 6b <- 1 {00} long get_m + (alu_set << 9) + (put_m << 18) + (6 << 27) 'SET 6,(HL) CBF6 6b <- 1 {00} long get_a + (alu_set << 9) + (put_a << 18) + (6 << 27) 'SET 6,A CBF7 6b <- 1 {00} long get_b + (alu_set << 9) + (put_b << 18) + (7 << 27) 'SET 7,B CBF8 7b <- 1 {00} long get_c + (alu_set << 9) + (put_c << 18) + (7 << 27) 'SET 7,C CBF9 7b <- 1 {00} long get_d + (alu_set << 9) + (put_d << 18) + (7 << 27) 'SET 7,D CBFA 7b <- 1 {00} long get_e + (alu_set << 9) + (put_e << 18) + (7 << 27) 'SET 7,E CBFB 7b <- 1 {00} long get_h + (alu_set << 9) + (put_h << 18) + (7 << 27) 'SET 7,H CBFC 7b <- 1 {00} long get_l + (alu_set << 9) + (put_l << 18) + (7 << 27) 'SET 7,L CBFD 7b <- 1 {00} long get_m + (alu_set << 9) + (put_m << 18) + (7 << 27) 'SET 7,(HL) CBFE 7b <- 1 {00} long get_a + (alu_set << 9) + (put_a << 18) + (7 << 27) 'SET 7,A CBFF 7b <- 1 '--------------------------------------------------------------------------------------------------------- '--------------------------------------------------------------------------------------------------------- dispatch_table_z80_dd_prefix {00} long undocumented {01} long undocumented {02} long undocumented {03} long undocumented {04} long undocumented {05} long undocumented {06} long undocumented {07} long undocumented {08} long undocumented {09} long get_bc + (double_add_ixy << 9) + (put_ixy << 18) '* ADD IX,BC DD09 IX <- IX + BC {0A} long undocumented {0B} long undocumented {0C} long undocumented {0D} long undocumented {0E} long undocumented {0F} long undocumented {10} long undocumented {11} long undocumented {12} long undocumented {13} long undocumented {14} long undocumented {15} long undocumented {16} long undocumented {17} long undocumented {18} long undocumented {19} long get_de + (double_add_ixy << 9) + (put_ixy << 18) '* ADD IX,DE DD19 IX <- IX + DE {1A} long undocumented {1B} long undocumented {1C} long undocumented {1D} long undocumented {1E} long undocumented {1F} long undocumented {20} long undocumented {21} long get_immediate_word + (put_ixy << 9) '* LD IX,word DD21word IX <- word {22} long get_bc + (0 << 9) + (0 << 18) 'LD (word),IX DD22word (word) <- IX {23} long get_ixy + (increment_word << 9) + (put_ixy << 18) '* INC IX DD23 IX <- IX + 1 {24} long undocumented {25} long undocumented {26} long undocumented {27} long undocumented {28} long undocumented {29} long get_ixy + (double_add_ixy << 9) + (put_ixy << 18) '* ADD IX,IX DD29 IX <- IX + IX {2A} long get_bc + (0 << 9) + (0 << 18) 'LD IX,(word) DD2Aword IX <- (word) {2B} long get_ixy + (decrement_word << 9) + (put_ixy << 18) '* DEC IX DD2B IX <- IX - 1 {2C} long undocumented {2D} long undocumented {2E} long undocumented {2F} long undocumented {30} long undocumented {31} long undocumented {32} long undocumented {33} long undocumented {34} long get_mem_ixy_idx + (increment_byte << 9) + (put_mem_ixy_idx<< 18) '* INC (IX+index) DD34index (IX+index) <- (IX+index) + 1 {35} long get_mem_ixy_idx + (decrement_byte << 9) + (get_mem_ixy_idx<< 18) '* DEC (IX+index) DD35index (IX+index) <- (IX+index) - 1 {36} long undocumented {37} long undocumented {38} long undocumented {39} long get_sp + (double_add_ixy << 9) + (put_ixy << 18) '* ADD IX,SP DD39 IX <- IX + SP {3A} long undocumented {3B} long undocumented {3C} long undocumented {3D} long undocumented {3E} long undocumented {40} long undocumented {41} long undocumented {42} long undocumented {43} long undocumented {44} long undocumented {45} long undocumented {46} long get_mem_ixy_idx + (put_b << 9) '* LD B,(IX+index) DD46index B <- (IX+index) {47} long undocumented {48} long undocumented {49} long undocumented {4A} long undocumented {4B} long undocumented {4C} long undocumented {4D} long undocumented {4E} long get_mem_ixy_idx + (put_c << 9) '* LD C,(IX+index) DD4Eindex C <- (IX+index) {4F} long undocumented {50} long undocumented {51} long undocumented {52} long undocumented {53} long undocumented {54} long undocumented {55} long undocumented {56} long get_mem_ixy_idx + (put_d << 9) '* LD D,(IX+index) DD56index D <- (IX+index) {57} long undocumented {58} long undocumented {59} long undocumented {5A} long undocumented {5B} long undocumented {5C} long undocumented {5D} long undocumented {5E} long get_mem_ixy_idx + (put_e << 9) '* LD E,(IX+index) DD5Eindex E <- (IX+index) {5F} long undocumented {60} long undocumented {61} long undocumented {62} long undocumented {63} long undocumented {64} long undocumented {65} long undocumented {66} long get_mem_ixy_idx + (put_h << 9) '* LD H,(IX+index) DD66index H <- (IX+index) {67} long undocumented {68} long undocumented {69} long undocumented {6A} long undocumented {6B} long undocumented {6C} long undocumented {6D} long undocumented {6E} long get_mem_ixy_idx + (put_l << 9) '* LD L,(IX+index) DD6Eindex L <- (IX+index) {6F} long undocumented {70} long get_b + (put_mem_ixy_idx << 9) '* LD (IX+index),B DD70index (IX+index) <- B {71} long get_c + (put_mem_ixy_idx << 9) '* LD (IX+index),C DD71index (IX+index) <- C {72} long get_d + (put_mem_ixy_idx << 9) '* LD (IX+index),D DD72index (IX+index) <- D {73} long get_e + (put_mem_ixy_idx << 9) '* LD (IX+index),E DD73index (IX+index) <- E {74} long get_h + (put_mem_ixy_idx << 9) '* LD (IX+index),H DD74index (IX+index) <- H {75} long get_l + (put_mem_ixy_idx << 9) '* LD (IX+index),L DD75index (IX+index) <- L {76} long get_bc + (put_mem_ixy_idx << 9) 'LD (IX+index),byte DD76indexbyte (IX+index) <- byte {77} long get_a + (put_mem_ixy_idx << 9) '* LD (IX+index),A DD77index (IX+index) <- A {78} long undocumented {79} long undocumented {7A} long undocumented {7B} long undocumented {7C} long undocumented {7D} long undocumented {7E} long get_mem_ixy_idx + (put_a << 9) '* LD A,(IX+index) DD7Eindex A <- (IX+index) {7F} long undocumented {80} long undocumented {81} long undocumented {82} long undocumented {83} long undocumented {84} long undocumented {85} long undocumented {86} long get_mem_ixy_idx + (alu_add << 9) + (put_a << 18) '* ADD A,(IX+index) DD86index A <- A + (IX+index) {87} long undocumented {88} long undocumented {89} long undocumented {8A} long undocumented {8B} long undocumented {8C} long undocumented {8D} long undocumented {8E} long get_mem_ixy_idx + (alu_add_with_carry << 9) + (put_a << 18) '* ADC A,(IX+index) DD8Eindex A <- A + (IX+index) + Carry {8F} long undocumented {90} long undocumented {91} long undocumented {92} long undocumented {93} long undocumented {94} long undocumented {95} long undocumented {96} long get_mem_ixy_idx + (alu_sub << 9) + (put_a << 18) '* SUB (IX+index) DD96index A <- A - (IX+index) {97} long undocumented {98} long undocumented {99} long undocumented {9A} long undocumented {9B} long undocumented {9C} long undocumented {9D} long undocumented {9E} long get_mem_ixy_idx + (alu_sub_with_borrow << 9) + (put_a << 18) '* SBC (IX+index) DD9Eindex A <- A - (IX+index) - Carry {9F} long undocumented {A0} long undocumented {A1} long undocumented {A2} long undocumented {A3} long undocumented {A4} long undocumented {A5} long undocumented {A6} long get_mem_ixy_idx + (alu_and << 9) + (put_a << 18) '* AND (IX+index) DDA6index A <- A AND (IX+index) {A7} long undocumented {A8} long undocumented {A9} long undocumented {AA} long undocumented {AB} long undocumented {AC} long undocumented {AD} long undocumented {AE} long get_mem_ixy_idx + (alu_xor << 9) + (put_a << 18) '* XOR (IX+index) DDAEindex A <- A XOR (IX+index) {AF} long undocumented {B0} long undocumented {B1} long undocumented {B2} long undocumented {B3} long undocumented {B4} long undocumented {B5} long undocumented {B6} long get_mem_ixy_idx + (alu_or << 9) + (put_a << 18) '* OR (IX+index) DDB6index A <- A OR (IX+index) {B7} long undocumented {B8} long undocumented {B9} long undocumented {BA} long undocumented {BB} long undocumented {BC} long undocumented {BD} long undocumented {BE} long get_mem_ixy_idx + (alu_sub << 9) + (fetch << 18) '* CP (IX+index) DDBEindex A - (IX+index) {BF} long undocumented {C0} long undocumented {C1} long undocumented {C2} long undocumented {C3} long undocumented {C4} long undocumented {C5} long undocumented {C6} long undocumented {C7} long undocumented {C8} long undocumented {C9} long undocumented {CA} long undocumented {CB} long get_bc + (0 << 9) + (0 << 18) 'RLC (IX+index) DDCBindex06 --- {CC} long undocumented {CD} long undocumented {CE} long undocumented {CF} long undocumented {D0} long undocumented {D1} long undocumented {D2} long undocumented {D3} long undocumented {D4} long undocumented {D5} long undocumented {D6} long undocumented {D7} long undocumented {D8} long undocumented {D9} long undocumented {DA} long undocumented {DB} long undocumented {DD} long undocumented {DE} long undocumented {DF} long undocumented {E0} long undocumented {E1} long get_bc + (0 << 9) + (0 << 18) 'POP IX DDE1 IXh <- (SP+1); IXl <- (SP); {E2} long undocumented {E3} long get_bc + (0 << 9) + (0 << 18) 'EX (SP),IX DDE3 IXh <-> (SP+1); IXl <-> (SP) {E4} long undocumented {E5} long get_bc + (0 << 9) + (0 << 18) 'PUSH IX DDE5 (SP-2) <- IXl; (SP-1) <- IXh {E6} long undocumented {E7} long undocumented {E8} long undocumented {E9} long get_ixy + (put_pc << 9) '* JP (IX) DDE9 PC <- IX {EA} long undocumented {EB} long undocumented {EC} long undocumented {ED} long undocumented {EE} long undocumented {EF} long undocumented {F0} long undocumented {F1} long undocumented {F2} long undocumented {F3} long undocumented {F4} long undocumented {F5} long undocumented {F6} long undocumented {F7} long undocumented {F8} long undocumented {F9} long get_ixy + (put_sp << 9) '* LD SP,IX DDF9 SP <- IX {FA} long undocumented {FB} long undocumented {FC} long undocumented {FD} long undocumented {FE} long undocumented {FF} long undocumented '--------------------------------------------------------------------------------------------------------- '--------------------------------------------------------------------------------------------------------- dispatch_table_z80_ddcb_prefix { {00} long get_bc + (0 << 9) + (put_iy << 18) 'RRC (IX+index) DDCBindex0E --- {00} long get_bc + (0 << 9) + (put_iy << 18) 'RL (IX+index) DDCBindex16 --- {00} long get_bc + (0 << 9) + (put_iy << 18) 'RL (IX+index) DDCBindex1E --- {00} long get_bc + (0 << 9) + (put_iy << 18) 'SLA (IX+index) DDCBindex26 --- {00} long get_bc + (0 << 9) + (put_iy << 18) 'SRA (IX+index) DDCBindex2E --- {00} long get_bc + (0 << 9) + (put_iy << 18) 'SRL (IX+index) DDCBindex3E --- {00} long get_bc + (0 << 9) + (put_iy << 18) 'BIT 0,(IX+index) DDCBindex46 Z flag <- NOT 0b {00} long get_bc + (0 << 9) + (put_iy << 18) 'BIT 1,(IX+index) DDCBindex4E Z flag <- NOT 1b {00} long get_bc + (0 << 9) + (put_iy << 18) 'BIT 2,(IX+index) DDCBindex56 Z flag <- NOT 2b {00} long get_bc + (0 << 9) + (put_iy << 18) 'BIT 3,(IX+index) DDCBindex5E Z flag <- NOT 3b {00} long get_bc + (0 << 9) + (put_iy << 18) 'BIT 4,(IX+index) DDCBindex66 Z flag <- NOT 4b {00} long get_bc + (0 << 9) + (put_iy << 18) 'BIT 5,(IX+index) DDCBindex6E Z flag <- NOT 5b {00} long get_bc + (0 << 9) + (put_iy << 18) 'BIT 6,(IX+index) DDCBindex76 Z flag <- NOT 6b {00} long get_bc + ( 0 << 9) + (put_iy << 18) 'BIT 7,(IX+index) DDCBindex7E Z flag <- NOT 7b {00} long get_bc + ( 0 << 9) + (put_iy << 18) 'RES 0,(IX+index) DDCBindex86 0b <- 0 {00} long get_bc + (0 << 9) + (put_iy << 18) 'RES 1,(IX+index) DDCBindex8E 1b <- 0 {00} long get_bc + (0 << 9) + (put_iy << 18) 'RES 2,(IX+index) DDCBindex96 2b <- 0 {00} long get_bc + (0 << 9) + (put_iy << 18) 'RES 3,(IX+index) DDCBindex9E 3b <- 0 {00} long get_bc + (0 << 9) + (put_iy << 18) 'RES 4,(IX+index) DDCBindexA6 4b <- 0 {00} long get_bc + (0 << 9) + (put_iy << 18) 'RES 5,(IX+index) DDCBindexAE 5b <- 0 {00} long get_bc + (0 << 9) + (put_iy << 18) 'RES 6,(IX+index) DDCBindexB6 6b <- 0 {00} long get_bc + (0 << 9) + (put_iy << 18) 'RES 7,(IX+index) DDCBindexBE 7b <- 0 {00} long get_bc + (0 << 9) + (put_iy << 18) 'SET 0,(IX+index) DDCBindexC6 0b <- 1 {00} long get_bc + (0 << 9) + (put_iy << 18) 'SET 1,(IX+index) DDCBindexCE 1b <- 1 {00} long get_bc + (0 << 9) + (put_iy << 18) 'SET 2,(IX+index) DDCBindexD6 2b <- 1 {00} long get_bc + (0 << 9) + (put_iy << 18) 'SET 3,(IX+index) DDCBindexDE 3b <- 1 {00} long get_bc + (0 << 9) + (put_iy << 18) 'SET 4,(IX+index) DDCBindexE6 4b <- 1 {00} long get_bc + (0 << 9) + (put_iy << 18) 'SET 5,(IX+index) DDCBindexEE 5b <- 1 {00} long get_bc + (0 << 9) + (put_iy << 18) 'SET 6,(IX+index) DDCBindexF6 6b <- 1 {00} long get_bc + (0 << 9) + (put_iy << 18) 'SET 7,(IX+index) DDCBindexFE 7b <- 1 }