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P2 - Minimising power usage in a COG (cpu core)

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  • jmgjmg Posts: 15,140
    evanh wrote: »
    ... Program 1 in particular is using less power with all cogs running! Working on it ...

    Hehe, can Parallax then claim a negative uA/MHz cost, for running more cogs ? ;)


  • Cluso99Cluso99 Posts: 18,066
    evanh wrote: »
    Cluso99 wrote: »
    I would still like to see the difference between a cog loop and a hubexec loop. The difference will show how much the hub ram is taking.
    Program 3 is equivalent to worst case hubexec.

    IMHO, not at all.

    Two cases at one frequency say 180MHz...
            org     0
            jmp     #@hubexec
    
            orgh    $1000
    hubexec jmp     #@hubexec
    
            org     0
            jmp     #@hubexec
    
            orgh
    hubexec add     pa,#1
            add     pa,#1
            add     pa,#1
            add     pa,#1
            add     pa,#1
            add     pa,#1
            add     pa,#1
            add     pa,#1
            add     pa,#1
            add     pa,#1
            add     pa,#1
            add     pa,#1
            add     pa,#1
            add     pa,#1
            add     pa,#1
            add     pa,#1
            jmp     #@hubexec
    
    The first case will only be exercising the hub ram once, then a stall until the window comes around again.
    The second case exercises the hub ram for 16 cycles before a stall. I'm not sure how many extra adds could fit in and still catch the next slot. I'll give this a try as soon as I can.

    What I'm interested in is the actual additional power the hubexec adds by reading the hub ram for code. Doing fifo, rnd, mul only skew the results. In fact I even wonder if the adds were nops if that would make a difference. Sometime in the future it may even be worth categorising the various instructions just for fun.
  • evanhevanh Posts: 15,126
    edited 2019-09-26 00:53
    Cluso,
    The difference between program 2 and program 3 tells you a worst case of that. Worse than practical of course. With program 1 in hubexec, the effect is not measurable at all.
  • jmgjmg Posts: 15,140
    edited 2019-09-26 01:03
    Cluso99 wrote: »
    What I'm interested in is the actual additional power the hubexec adds by reading the hub ram for code. Doing fifo, rnd, mul only skew the results...
    evanh wrote: »
    Cluso,
    The difference between program 2 and program 3 tells you a worst case of that. Worse than practical of course. With program 1 in hubexec, the effect is not measurable at all.

    I think the power adder is not so much 'hubexec' as the memory+bus usage, and there, the fully loaded FIFO test should be worst case. (100% slots used)
    I'm not sure adding more cogs also running their FIFOs would increment much, as the memory is already 100% active and RW-bus is enabled ?
    Maybe there is a small more local BUS Buffer to COG adder for N-FIFOs operating ?

    I guess as well as the 7 more COGS idling test evanh is working on, another one could be done with 7 more cogs all running FIFOs, as an extreme corner case ?
  • evanhevanh Posts: 15,126
    edited 2019-09-26 01:41
    Don't worry, eight cogs all working their FIFOs is plenty more power. I've just done the revA and it is hitting 1.7 amps on VDD at 250 MHz. And that's with a drooping (Because of the inline current meter) 1.7 volt supply too.
  • jmgjmg Posts: 15,140
    edited 2019-09-26 02:15
    evanh wrote: »
    Don't worry, eight cogs all working their FIFOs is plenty more power. I've just done the revA and it is hitting 1.7 amps on VDD at 250 MHz. And that's with a drooping (Because of the inline current meter) 1.7 volt supply too.
    Wow, suggests not much base load effect from RAM-enabled power then ?

    Rev A 250MHz from your earlier numbers gives :

    843-704 = 139mA == Activity adder Pgm3-Pgm1
    Added activity current for 7 more cogs (1700-843)/7 = 122.42mA/ added COG
    So the adder for COGS is quite similar, & does not seem to care much if other COGS already access the SRAM. (maybe a modest ~14% saving from already active effect ?)

    Edit: That was assuming the disabled COG started at Pgm1 Icc, but the below suggests a 10.285mA skew, which drops any common-ram-enabled effect to closer to 5%, even more modest.

  • jmgjmg Posts: 15,140
    evanh wrote: »
    ...
    EDIT: Yep, I'm pretty certain I've got that one verified. With program #1, one cog running on the revB chip at 360 MHz it uses 405 mA, while with eight cogs it uses only 333 mA. Pretty much same a one cog at 300 MHz.
    ... but the revB chip sure is. It appears an idle cog uses less power than a stopped cog on the revB silicon.

    Hmm, so that's (405-333)/7 = -10.285mA per added idling COG, for a final average of 41.625mA per idling code
    I guess that depends on what STOP does, exactly. Looks like more clock gating is enabled by WAIT than by STOP ?
    ( A rev C part could do more to gate each COG-clock during STOP and WAIT ?)

    I have seen 8bit MCUs draw quite differing currents during reset active, depending on their design & it can vary from idle currents.

    What is the RevB Reset active current ? Maybe 73.6 mA ?
  • evanhevanh Posts: 15,126
    edited 2019-09-26 02:22
    I've unplugged it. Everything is a mess at the moment. I couldn't get program3 to 250 MHz. The 1.8 v VDD regulator is collapsing. :( EDIT: Or the USB is ...
  • evanhevanh Posts: 15,126
    Okay, looking at the schematic for the revB board .... the USB power switches have adjustable current limits. And AUX one is much higher limit than the programming one. So a second cable is a quick fix.

    I'm using a mains powered USB hub, so the programming cable has same power capacity as the aux cable. I'll look at adjusting the current limit of the USB power switch for the programming port so I don't have to have two cables ...
  • evanhevanh Posts: 15,126
    jmg wrote: »
    What is the RevB Reset active current ? Maybe 73.6 mA ?
    Goes down to 60 uA, lower than RCSLOW.

  • cgraceycgracey Posts: 14,133
    evanh wrote: »
    jmg wrote: »
    What is the RevB Reset active current ? Maybe 73.6 mA ?
    Goes down to 60 uA, lower than RCSLOW.

    Once the chip comes out of reset, though, the current draw is about 31mA, while cog 0 runs the booter code. It was 72mA on the Rev A silicon.
  • evanhevanh Posts: 15,126
    edited 2019-09-26 03:39
    Right, yep, I've noticed 33 mA regularly.

    Okay, I've completed the 8-cog testing. Some strange is happening above 320 MHz on program 3, the current drops markedly so by 360 MHz it is down to 1.2 A, I'm assuming it is crashing in some manner.

    PS: The volt readings at the bottom of the tables shows VDD at the chip side of the current meter when at the greatest load of that column.
    =====================
       One Cog Running
    =====================
            |      Prop2 revA (VDD = 1.83 V)            Prop2 revB (VDD = 1.855 V)
            |    PGM0     PGM1     PGM2     PGM3       PGM0     PGM1     PGM2     PGM3  
    --------|---------------------------------------------------------------------------
    RCSLOW  |   107 uA   104 uA   110 uA   116 uA      83 uA    79 uA    87 uA    96 uA 
    RCFAST  |  73.6 mA  70.3 mA  78.6 mA  84.7 mA    33.3 mA  29.4 mA  39.2 mA  47.4 mA 
     50 MHz |   157 mA   150 mA   168 mA   181 mA    66.2 mA  58.3 mA  78.4 mA  94.1 mA 
    100 MHz |   309 mA   295 mA   330 mA   355 mA     132 mA   116 mA   156 mA   187 mA 
    180 MHz |   542 mA   518 mA   578 mA   621 mA     234 mA   206 mA   277 mA   331 mA 
    250 MHz |   736 mA   704 mA   783 mA   843 mA     323 mA   284 mA   380 mA   455 mA 
    300 MHz |   869 mA   832 mA   922 mA   994 mA     384 mA   339 mA   453 mA   540 mA 
    360 MHz |            982 mA                       459 mA   405 mA   535 mA   641 mA 
            |           1.755 V   1.76 V  1.755 V    1.817 V   1.82 V   1.81 V  1.802 V
    
    ========================
       Eight Cogs Running
    ========================
            |      Prop2 revA (VDD = 1.83 V)             Prop2 revB (VDD = 1.855 V)
            |    PGM0     PGM1     PGM2     PGM3       PGM0     PGM1     PGM2     PGM3  
    --------|---------------------------------------------------------------------------
    RCSLOW  |
    RCFAST  |    98 mA  70.4 mA   129 mA   180 mA    56.0 mA  24.0 mA   102 mA   167 mA
     50 MHz |   210 mA   151 mA   276 mA   384 mA     111 mA  47.7 mA   201 mA   331 mA 
    100 MHz |   411 mA   296 mA   537 mA   744 mA     220 mA  95.0 mA   395 mA   643 mA 
    180 MHz |   714 mA   520 mA   927 mA  1273 mA     389 mA   169 mA   689 mA  1106 mA 
    250 MHz |   967 mA   708 mA  1244 mA  1693 mA     533 mA   233 mA   932 mA  1479 mA 
    300 MHz |  1139 mA   836 mA                       634 mA   278 mA  1098 mA  1730 mA 
    360 MHz |            985 mA                       752 mA   334 mA  1186 mA  
            |  1.745 V  1.756 V  1.737 V  1.704 V    1.795 V  1.828 V  1.763 V  1.718 V 
    
  • jmgjmg Posts: 15,140
    cgracey wrote: »
    evanh wrote: »
    jmg wrote: »
    What is the RevB Reset active current ? Maybe 73.6 mA ?
    Goes down to 60 uA, lower than RCSLOW.

    Once the chip comes out of reset, though, the current draw is about 31mA, while cog 0 runs the booter code. It was 72mA on the Rev A silicon.

    It would be useful to add a Manhatten current plot, like in P1 data, for P2 datasheet, showing as it comes out of reset, currents and durations.
  • jmgjmg Posts: 15,140
    evanh wrote: »
    jmg wrote: »
    What is the RevB Reset active current ? Maybe 73.6 mA ?
    Goes down to 60 uA, lower than RCSLOW.
    That's good. I was thinking RCFAST was running, but now I recall Chip runs a short exit-delay on RCSLOW, so that's all that needs to be alive at reset.

  • evanhevanh Posts: 15,126
    jmg wrote: »
    It would be useful to add a Manhatten current plot, like in P1 data, for P2 datasheet, showing as it comes out of reset, currents and durations.
    I did a rough one for the revA chip a while back. The static transition was somewhat guessed at though.
  • evanhevanh Posts: 15,126
    jmg wrote: »
    evanh wrote: »
    jmg wrote: »
    What is the RevB Reset active current ? Maybe 73.6 mA ?
    Goes down to 60 uA, lower than RCSLOW.
    That's good. I was thinking RCFAST was running, but now I recall Chip runs a short exit-delay on RCSLOW, so that's all that needs to be alive at reset.
    The revA chip drops to 40 uA with reset held. So the whole clock tree is stopped I'm thinking. So that is the static leakage current.

  • evanhevanh Posts: 15,126
    evanh wrote: »
    ... Some strange is happening above 320 MHz on program 3, the current drops markedly so by 360 MHz it is down to 1.2 A, I'm assuming it is crashing in some manner.
    I think the problem is my leads to the current meter. They're cheap. I'll make something heavier ...
  • well thats interesting
  • evanhevanh Posts: 15,126
    edited 2019-11-23 03:01
    Hmm, the high end readings are not particularly reliable. As the chip heats up, the current drops quite substantially. I've been able to monitor program 3 operating with eight cogs at 360 MHz, and appears to peak to a full 2.0 amps but quickly drops away below 1.9 amps.

    EDIT: Retested results for revB - https://forums.parallax.com/discussion/comment/1482622/#Comment_1482622

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