---------------------------------------------------------------------- First RDxxxx is to sync to the hub RAM egg beater Stall cycle near start of RDFAST only, not RDxxxx Key a = pre-read cycle b = post-read cycle s = stall cycle for RDFAST w = wait cycle due to egg beater f = FIFO stall cycle x = other instruction cycle ! = FIFO hub RAM read cycle ---------------------------------------------------------------------- RDFAST best-case, start address slice = 0 WAITX minimum for valid RDxxxx data RDFAST to RDxxxx best-case, slice difference = 3 567601234567012345670123456701234567012345670 | !!!!!!!!!!!!!!!!!!!| cycles instr aaawwwwwwwrbbbbb | | | RDxxxx aaasrbbbbb | | xx | | 2 RDFAST D[31]=1 xxxxxxx | | 7 WAITX #5 aaafffffffffffrbbbbb 20 RDxxxx ---------------------------------------------------------------------- RDFAST best-case, start address slice = 0 WAITX maximum for best-case RDxxxx, valid data RDFAST to RDxxxx best-case, slice difference = 3 567601234567012345670123456701234567012345670 | !!!!!!!!!!!!!!!!!!!| cycles instr aaawwwwwwwrbbbbb | | RDxxxx aaasrbbbbb | xx | 2 RDFAST D[31]=1 xxxxxxxxxxxxxxxxxx | 18 WAITX #16 aaarbbbbb 9 RDxxxx ---------------------------------------------------------------------- RDFAST best-case, start address slice = 0 WAITX minimum for valid RDxxxx data RDFAST to RDxxxx worst-case, slice difference = 2 5676012345670123456701234567012345670123456701234567 | !!!!!!!!!!!!!!!!!!! | cycles instr aaawwwwwwwrbbbbb | | | | RDxxxx aaasrbbbbb | | | xx | | | 2 RDFAST D[31]=1 xxxxxxx | | | 7 WAITX #5 aaafffffffffffwwwwwwwrbbbbb 27 RDxxxx ------------------------------------------------------------------------- RDFAST best-case, start address slice = 0 WAITX maximum for best-case RDxxxx, valid data RDFAST to RDxxxx worst-case, slice difference = 2 5676012345670123456701234567012345670123456701234567 | !!!!!!!!!!!!!!!!!!! | cycles instr aaawwwwwwwrbbbbb | | RDxxxx aaasrbbbbb | xx | 2 RDFAST D[31]=1 xxxxxxxxxxxxxxxxxxxxxxxxx | 25 WAITX #23 aaarbbbbb 9 RDxxxx ------------------------------------------------------------------------- RDFAST worst-case, start address slice = 0 WAITX minimum for valid RDxxxx data RDFAST to RDxxxx best-case, slice difference = 3 5670123456701234567012345670123456701234567012345670 | | !!!!!!!!!!!!!!!!!!!| cycles instr aaawwwwwwwrbbbbb | | | RDxxxx aaaswwwwwwwrbbbbb | | xx | | 2 RDFAST D[31]=1 xxxxxxxxxxxxxx | | 14 WAITX #12 aaafffffffffffrbbbbb 20 RDxxxx ------------------------------------------------------------------------- RDFAST worst-case, start address slice = 0 WAITX maximum for best-case RDxxxx, valid data RDFAST to RDxxxx best-case, slice difference = 3 5670123456701234567012345670123456701234567012345670 | | !!!!!!!!!!!!!!!!!!!| cycles instr aaawwwwwwwrbbbbb | | RDxxxx aaaswwwwwwwrbbbbb | xx | 2 RDFAST D[31]=1 xxxxxxxxxxxxxxxxxxxxxxxxx | 25 WAITX #23 aaarbbbbb 9 RDxxxx ------------------------------------------------------------------------- RDFAST worst-case, start address slice = 0 WAITX minimum for valid RDxxxx data RDFAST to RDxxxx worst-case, slice difference = 2 56701234567012345670123456701234567012345670123456701234567 | | !!!!!!!!!!!!!!!!!!! | cycles instr aaawwwwwwwrbbbbb | | | | RDxxxx aaaswwwwwwwrbbbbb | | | xx | | | 2 RDFAST D[31]=1 xxxxxxxxxxxxxx | | | 14 WAITX #12 aaafffffffffffwwwwwwwrbbbbb 27 RDxxxx -------------------------------------------------------------------------------- RDFAST worst-case, start address slice = 0 WAITX maximum for best-case RDxxxx, valid data RDFAST to RDxxxx worst-case, slice difference = 2 56701234567012345670123456701234567012345670123456701234567 | | !!!!!!!!!!!!!!!!!!! | cycles instr aaawwwwwwwrbbbbb | | RDxxxx aaaswwwwwwwrbbbbb | xx | 2 RDFAST D[31]=1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx | 32 WAITX #30 aaarbbbbb 9 RDxxxx --------------------------------------------------------------------------------