Propeller II
Title: | Propeller II |
Author: | 64.167.32.214 |
Published: | Wed, 27 Oct 2010 16:10:38 GMT |
Feature |
Quantity |
Comments |
Forum post link |
Cogs |
8 v |
COG instructions pipelined (1 per clock effective) Hub instructions take 2 clocks, you can fit 6 regular instructions between successive hub accesses. Quad-long read (four longs in one hub instruction) is on the slate for implementation as well |
8 COGs post (other mentions in the newer posts from Aug 2008 to Sept 2008) Other data: Chip post |
HUB access every 8 clocks |
Chip post |
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512 longs per COG (same number, but more will be available for coding than the Prop 1, 506 vs 496) |
Chip post |
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256 entry 16bit CLUT, used with VSU to get 16bit color data per pixel. Also accessible as 128 longs of general storage. "The CLUT will not be rewritten during a cog reload, so it will retain its prior contents." |
Chip post Chip post |
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Memory |
RAM 128K v |
HUB memory Layout Engineer Beau Schwabe assures room on the die for at 128K, and some rearranging may allow for 256K. |
Beau Post |
ROM 32K v |
ROM includes entire development system. (No need for PC!) Released info from Parallax says 32K. |
128k ROM: Chip post Other: Chip post |
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HUB Address Space |
32bit v |
In order to have 128KB RAM and 32KB ROM, they had to expand. They decided to go all the way to 32bit. |
Chip post |
I/Os |
92 v |
Most recent posts say it's 92 now. "each pair of adjacent Prop II I/Os has a high-speed comparator between them that can toggle at 50MHz" |
Chip post Chip post Chip post |
ADC/DAC |
92 v |
"EVERY pin will have one these babies in it, along with a comparator, a delta-sigma ADC, a delta-sigma DAC, a high speed signal/video 75-ohm DAC, pull-ups/downs, slew control, float/weak/strong HIGH/LOW combos, schmitt input w/feedback, crystal oscillator, and a few other things" |
Chip post |
Serializer / Deserializer |
? |
"I just need to narrow down what kinds of demodulation we should support. Manchester and NRZ come to mind" |
Chip post |
PLL speed |
160Mhz ? |
They hope to reach 160Mhz. |
Chip post |
Packaging |
TQFP-128 (14x14mm) ? QFN-128 (12x12mm) ? |
Chip post Chip post |
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Process |
180nm v |
Beau post |
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Pins |
128 |
92 I/Os v 8 VP0-7 power 1 per 8 I/Os (1.8v - 3.3v) (more functional at 3.3v) v 8 GP0-7 grounds 1 per 8 I/Os v 8 VDD 1.8v Core power v 8 GND v 1 RESn Reset v 2 XI/XO Clock v 1 BOEn Brown Out v |
VIO pins: Chip post Pin arrangement Image from Beau: Image |