Propeller 2 Instructions
Title:Propeller 2 Instructions
Author:74.126.40.138
Published:Fri, 15 Apr 2011 20:23:33 GMT

This page covers the proposed new Instructions for the Next Propeller chip.


The new chip will have all the the existing instructions with the same binary layout. New instructions have been mapped into the unused slots. (Reference = Chip Gracey Post)

Instructions:


Other related info:
In this post, Chip mentions a divider circuit. The concept is that you would write your values to registers and then some number of clocks later read the results back out. This same concept is mentioned for square root elsewhere in the same thread.

This post mentions: CORDIC, MAC/MACS, REPeat, indirect register addressing, and hub memory pointers.
Chip mentions in other posts some instructions called SETINDA/B, and associated INDA/B registers. These are the "indirect register addressing" feature. This post has some more info on these.
He, also, mentions the PTRA/B and SETPTRA/B instructions when talking about the post/pre increment/decrement feature enhancement to RDxxxx/WRxxxx. These are the "hub memory pointers" feature.
It's unknown at this time if the PTRA/B and INDA/B registers are just more special registers at the end of cog memory (most likely) or if they are something new.