dat orgh 0 ' Set up fancy debug ISR for cog 0 org hubset #$FF 'set clock to 80MHz wrlong newjmp,##$FFFF8 'set jmp to isr, instead of just reti0 coginit #1,#@start 'restart cog 1 with target program coginit #0,#@start1 newjmp jmp #isr 'this jmp instruction goes at $FFFFC ' This program demonstrates single-stepping. ' You'll need to connect a logic analyzer to p4..p0. org start mov ijmp1,#int1 'set interrupt vectors mov ijmp2,#int2 mov ijmp3,#int3 getct t1 'set initial ct1 event addct1 t1,time1 getct t2 'set initial ct2 event addct2 t2,time2 getct t3 'set initial ct3 event addct3 t3,time3 setint1 #1 'ct1 interrupt on int1 setint2 #2 'ct2 interrupt on int2 setint3 #3 'ct3 interrupt on int3 bmask dira,#$F 'make pins 15..0 outputs loop drvl #4 'this routine is getting single-stepped skip #%10010011 drvnot #6 drvnot #6 brk #0' drvnot #6 drvnot #6 drvnot #6 drvnot #6 drvnot #6 drvnot #6 ll'brk #0 brk #0 drvh #4 drvh #5 drvl #5 bp jmp #loop int1 addct1 t1,time1 'int1..int3, all getting single-stepped outnot #1 outnot #1 reti1 int2 addct2 t2,time2 outnot #2 outnot #2 reti2 int3 addct3 t3,time3 outnot #3 outnot #3 reti3 time1 long 20001 time2 long 20002 time3 long 20003 t1 res 1 t2 res 1 t3 res 1 x res 1 ' cog0 program makes async debug interrupt in cog1 org start1 waitx ##201 getint #1 drvnot #7 drvnot #7 jmp #start1 ' Put this fancy debug ISR into hub exec area orgh $400 isr outh #0 'this is the single-step interrupt routine ' getint 200 wz ' shr 200,#24 ' setbyte outa,200,#1 ' setbyte outa,inb,#1 ' setbyte outa,iret1,#0 outl #0 brk #$40 'enable async breakpoint ' brk #$20 'enable break instruction ' brk ##bp<<8 + $10 'enable address breakpoint ' brk #$0F 'enable single-stepping in int3/int2/int1/main reti0