Hub RAM read & write timing (version 2, December 2020) A hub RAM read involves three separate stages: a read command is sent from cog to hub, the hub RAM is read and the read data are sent from hub to cog. There is a fixed pre-read time of 3 cycles, a variable read time due to the egg beater of 1-8 cycles and a fixed post-read time of 5 cycles. These are denoted by the letters a, r and b, respectively, in the tables below where each letter represents one cycle. The shortest read of 9 cycles is given by aaarbbbbb and the longest of 16 cycles by aaarrrrrrrrbbbbb. A hub RAM write also has three stages: write data are sent from cog to hub, a wait for the hub slot and an acknowledgement sent from hub to cog. There is a fixed pre-wait time of 2 cycles, a variable wait of 0-7 cycles and a fixed post-wait of 1 cycle, denoted by the letters c, w and d, respectively. The actual write takes place a few clocks later but does not delay the cog. The shortest write of 3 cycles is given by ccd and the longest of 10 cycles by ccwwwwwwwd. If a hub RAM read or write is followed by another and the phase or egg beater slice difference between the two is known, then in most cases it is possible to use the time that would be wasted on egg beater delays to run one or more instructions between the hub accesses. This is easy to see in the tables, in which these intermediate instructions are denoted by i1, i2, etc., * indicating that one can be 3 cycles long. The initial read or write, shown with worst-case timing but of unknown duration, synchronizes subsequent reads or writes to the egg beater. Cycle lengths are given from the second hub access onwards and assume no long crossing that would add an extra cycle. ---------------------------------------------------------------------------- hub RAM timings for read - write - read - write (no long crossings) slice 012345670123456701234567012345670 . : . : cycles rd0 aaarrrrrrrrbbbbb : . : ? wr0 . ccd . : 3 rd0 . :aaarrrrrbbbbb : 13 wr0 . : . ccd 3 . : . : ins rd0_____________wr0i1i2rd0______wr0 slice 0123456701234567012345670123456701 . : . : cycles rd0 aaarrrrrrrrbbbbb : . : ? wr0 . ccd . : 3 rd1 . :aaarrrrrrbbbbb : 14 wr1 . : . ccd 3 . : . : ins rd0_____________wr0i1i2*rd1______wr1 slice 01234567012345670123456701234567012 . : . : cycles rd0 aaarrrrrrrrbbbbb : . : ? wr1 . ccwd . : 4 rd1 . :aaarrrrrbbbbb : 13 wr2 . : . ccc: 4 . : . : ins rd0_____________wr1_i1i2rd1______wr2 slice 012345670123456701234567012345670123 . : . : cycles rd0 aaarrrrrrrrbbbbb : . : ? wr2 . ccwwd . : 5 rd1 . :aaarrrrbbbbb : 12 wr3 . : . ccwwd 5 . : . : ins rd0_____________i1wr2i2*rd1______i1wr3 slice 0123456701234567012345670123456701234 . : . : cycles rd0 aaarrrrrrrrbbbbb : . : ? wr3 . ccwwwd . : 6 rd1 . :aaarrrbbbbb : 11 wr4 . : . cccww: 6 . : . : ins rd0_____________i1*wr3i2rd1______i1*wr4 slice 01234567012345670123456701234567012345 . : . : cycles rd0 aaarrrrrrrrbbbbb : . : ? wr4 . ccwwwwd . : 7 rd1 . :aaarrbbbbb : 10 wr5 . : . ccwwwwd 7 . : . : ins rd0_____________i1i2wr4rd1_______i1i2wr5 slice 012345670123456701234567012345670123456 . : . : cycles rd0 aaarrrrrrrrbbbbb : . : ? wr5 . ccwwwwwd . : 8 rd1 . :aaarbbbbb : 9 wr6 . : . ccwwwwwd 8 . : . : ins rd0_____________i1i2*wr5rd1______i1i2*wr6 slice 012345670123456701234567012345670123456701234567 . : . : cycles rd0 aaarrrrrrrrbbbbb : . : ? wr6 . ccwwwwwwd . : 9 rd1 . :aaarrrrrrrrbbbbb : 16 wr7 . : . ccwwwwwwd 9 . : . : ins rd0_____________i1i2i3wr6i4i5i6*rd1______i1i2i3wr7 slice 0123456701234567012345670123456701234567012345670 . : . : cycles rd0 aaarrrrrrrrbbbbb : . : ? wr7 . ccwwwwwwwd . : 10 rd1 . :aaarrrrrrrbbbbb : 15 wr0 . : . ccwwwwwwwd 10 . : . : ins rd0_____________i1i2i3*wr7i4i5i6rd1______i1i2i3*wr0 ---------------------------------------------------------------------------- hub RAM timings for read - write - read - write (long crossings) slice 01234567012345670123456701234567012345670123456701 .. :: .. :: cycles rd01 aaarrrrrrrrrbbbbb :: .. :: ? wr01 .. ccwwwwwwwwd .. :: 11 rd01 .. ::aaarrrrrbbbbb :: 13 wr01 .. :: .. ccwwwwwwwwd 11 .. :: .. :: ins rd01_____________i1i2i3*wr01i4*rd01______i1i2i3*wr01 slice 012345670123456701234567012345670123456701234567012 .. :: .. :: cycles rd01 aaarrrrrrrrrbbbbb :: .. :: ? wr01 .. ccwwwwwwwwd .. :: 11 rd12 .. ::aaarrrrrrbbbbb :: 14 wr12 .. :: .. ccwwwwwwwwd 11 .. :: .. :: ins rd01_____________i1i2i3*wr01i4i5rd12______i1i2i3*wr12 ---------------------------------------------------------------------------- hub RAM timings for read - read - read - read (no long crossings) slice 01234567012345670123456701234567012345670123456701234567012345 . . . . cycles rd0 aaarrrrrrrrbbbbb . . . ? rd0 . aaarrrrrrrrbbbbb . . 16 rd0 . . aaarrrrrrrrbbbbb . 16 rd0 . . . aaarrrrrrrrbbbbb 16 . . . . ins rd0_____________i1i2i3*rd0______i1i2i3*rd0______i1i2i3*rd0______ slice 01234567012345670123456701234567012345670 . . . . cycles rd0 aaarrrrrrrrbbbbb . . . ? rd1 . aaarbbbbb . . 9 rd2 . . aaarbbbbb . 9 rd3 . . aaarbbbbb 9 . . . . ins rd0_____________rd1______rd2______rd3______ slice 01234567012345670123456701234567012345670123 . . . . cycles rd0 aaarrrrrrrrbbbbb . . . ? rd2 . aaarrbbbbb . . 10 rd4 . . aaarrbbbbb . 10 rd6 . . . aaarrbbbbb 10 . . . . ins rd0_____________rd2_______rd4_______rd6_______ slice 01234567012345670123456701234567012345670123456 . . . . cycles rd0 aaarrrrrrrrbbbbb . . . ? rd3 . aaarrrbbbbb . . 11 rd6 . . aaarrrbbbbb . 11 rd1 . . . aaarrrbbbbb 11 . . . . ins rd0_____________i1rd3______i1rd6______i1rd1______ slice 01234567012345670123456701234567012345670123456701 . . . . cycles rd0 aaarrrrrrrrbbbbb . . . ? rd4 . aaarrrrbbbbb . . 12 rd0 . . aaarrrrbbbbb . 12 rd4 . . . aaarrrrbbbbb 12 . . . . ins rd0_____________i1*rd4______i1*rd0______i1*rd4______ slice 01234567012345670123456701234567012345670123456701234 . . . . cycles rd0 aaarrrrrrrrbbbbb . . . ? rd5 . aaarrrrrbbbbb . . 13 rd2 . . aaarrrrrbbbbb . 13 rd7 . . . aaarrrrrbbbbb 13 . . . . ins rd0_____________i1i2rd5______i1i2rd2______i1i2rd7______ slice 01234567012345670123456701234567012345670123456701234567 . . . . cycles rd0 aaarrrrrrrrbbbbb . . . ? rd6 . aaarrrrrrbbbbb . . 14 rd4 . . aaarrrrrrbbbbb . 14 rd2 . . . aaarrrrrrbbbbb 14 . . . . ins rd0_____________i1i2*rd6______i1i2*rd4______i1i2*rd2______ slice 01234567012345670123456701234567012345670123456701234567012 . . . . cycles rd0 aaarrrrrrrrbbbbb . . . ? rd7 . aaarrrrrrrbbbbb . . 15 rd6 . . aaarrrrrrrbbbbb . 15 rd5 . . . aaarrrrrrrbbbbb 15 . . . . ins rd0_____________i1i2i3rd7______i1i2i3rd6______i1i2i3rd5______ ---------------------------------------------------------------------------- hub RAM timings for read - read - read - read (long crossings) slice 01234567012345670123456701234567012345670123456701234567012345 .. .. .. .. cycles rd01 aaarrrrrrrrrbbbbb .. .. .. ? rd01 .. aaarrrrrrrrbbbbb .. .. 16 rd01 .. .. aaarrrrrrrrbbbbb .. 16 rd01 .. .. .. aaarrrrrrrrbbbbb 16 .. .. .. .. ins rd01_____________i1i2i3rd01______i1i2i3rd01______i1i2i3rd01_____ slice 01234567012345670123456701234567012345670123456701234567012345670 .. .. .. .. cycles rd01 aaarrrrrrrrrbbbbb .. .. .. ? rd12 .. aaarrrrrrrrrbbbbb .. .. 17 rd23 .. .. aaarrrrrrrrrbbbbb .. 17 rd34 .. .. .. aaarrrrrrrrrbbbbb 17 .. .. .. .. ins rd01_____________i1i2i3*rd12______i1i2i3*rd23______i1i2i3*rd34______ ---------------------------------------------------------------------------- hub RAM timings for write - write - write - write (no long crossings) slice 012345670123456701234567012345670 : : : : cycles wr0 ccwwwwwwwd : : : ? wr0 :ccwwwwwd : : 8 wr0 : :ccwwwwwd : 8 wr0 : : :ccwwwwwd 8 : : : : ins wr0_______i1i2*wr0i1i2*wr0i1i2*wr0 slice 012345670123456701234567012345670123 : : : : cycles wr0 ccwwwwwwwd : : : ? wr1 ccwwwwwwd : : 9 wr2 : :ccwwwwwwd : 9 wr3 : : :ccwwwwwwd 9 : : : : 9 ins wr0______i1i2i3wr1i1i2i3wr2i1i2i3wr3 slice 012345670123456701234567012345670123456 : : : : cycles wr0 ccwwwwwwwd : : : ? wr2 :ccwwwwwwwd : : 10 wr4 : :ccwwwwwwwd : 10 wr6 : : :ccwwwwwwwd 10 : : : : ins wr0_______i1i2i3*wr2i1i2i3*wr4i1i2i3*wr6 slice 012345670123456701 : : : : cycles wr0 cccwwwwwwd : : : ? wr3 :ccd : : 3 wr6 : :ccd : 3 wr1 : : :ccd 3 : : : : ins wr0_______wr3wr6wr1 slice 012345670123456701234 : : : : cycles wr0 ccwwwwwwwd : : : ? wr4 :ccwd : : 4 wr0 : :ccwd : 4 wr4 : : :ccwd 4 ins wr0_______wr4_wr0_wr4_ slice 012345670123456701234567 : : : : cycles wr0 ccwwwwwwwd : : : ? wr5 :ccwwd : : 5 wr2 : :ccwwd : 5 wr7 : : :ccwwd 5 ins wr0_______i1wr5i1wr2i1wr7 slice 012345670123456701234567012 : : : : cycles wr0 ccwwwwwwwd : : : ? wr6 :ccwwwd : : 6 wr4 : :ccwwwd : 6 wr2 : : :ccwwwd 6 ins wr0_______i1*wr6i1*wr4i1*wr2 slice 012345670123456701234567012345 : : : : cycles wr0 ccwwwwwwwd : : : ? wr7 :ccwwwwd : : 7 wr6 : :ccwwwwd : 7 wr5 : : :ccwwwwd 7 ins wr0_______i1i2wr7i1i2wr6i1i2wr5 ---------------------------------------------------------------------------- hub RAM timings for write - write - write - write (long crossings) slice 0123456701234567012345670123456701 :: :: :: :: cycles wr01 ccwwwwwwwwd :: :: :: ? wr01 ::ccwwwwwd :: :: 8 wr01 :: ::ccwwwwwd :: 8 wr01 :: :: ::ccwwwwwd 8 :: :: :: :: ins wr01_______i1i2wr01i1i2wr01i1i2wr01 slice 0123456701234567012345670123456701234 :: :: :: :: cycles wr01 ccwwwwwwwwd :: :: :: ? wr12 ::ccwwwwwwd :: :: 9 wr23 :: ::ccwwwwwwd :: 9 wr34 :: :: ::ccwwwwwwd 9 :: :: :: :: 9 ins wr01______i1i2*wr12i1i2*wr23i1i2*wr34 ----------------------------------------------------------------------------