CTRA and CTRB Register Fields | ||||||
---|---|---|---|---|---|---|
31 |
30..26 |
25..23 |
22..15 |
14..9 |
8..6 |
5..0 |
- |
CTRMODE |
PLLDIV |
- |
BPIN |
- |
APIN |
PLLDIV Field Options | ||||||||
---|---|---|---|---|---|---|---|---|
PLLDIV |
%000 |
%001 |
%010 |
%011 |
%100 |
%101 |
%110 |
%111 |
Output |
VCO ÷ 128 |
VCO ÷ 64 |
VCO ÷ 32 |
VCO ÷ 16 |
VCO ÷ 8 |
VCO ÷ 4 |
VCO ÷ 2 |
VCO ÷ 1 |
Counter Modes (CTRMODE Field Values) | ||||
---|---|---|---|---|
CTRMODE |
Description |
Accumulate FRQx to PHSx |
APIN Output* |
BPIN Output* |
%00000 |
Counter disabled (off) |
0 (never) |
0 (none) |
0 (none) |
Phase-Locked Loop Modes |
||||
%00001 |
PLL internal (video mode) |
1 (always) |
0 |
0 |
%00010 |
PLL single-ended |
1 |
PLLx |
0 |
%00011 |
PLL differential |
1 |
PLLx |
!PLLx |
Numerically Controlled Oscillator Modes |
||||
%00100 |
NCO single-ended |
1 |
PHSx[31] |
0 |
%00101 |
NCO differential |
1 |
PHSx[31] |
!PHSx[31] |
Duty Modes |
||||
%00110 |
DUTY single-ended |
1 |
PHSx |
0 |
%00111 |
DUTY differential |
1 |
PHSx |
!PHSx-Carry |
Positive Detector Modes |
||||
%01000 |
POS detector |
A1 |
0 |
0 |
%01001 |
POS detector with feedback |
A1 |
0 |
!A1 |
%01010 |
POSEDGE detector |
A1 & !A2 |
0 |
0 |
%01011 |
POSEDGE detector w/ feedback |
A1 & !A2 |
0 |
!A1 |
Negative Detector Modes |
||||
%01100 |
NEG detector |
!A1 |
0 |
0 |
%01101 |
NEG detector with feedback |
!A1 |
0 |
!A1 |
%01110 |
NEGEDGE detector |
!A1 & A2 |
0 |
0 |
%01111 |
NEGEDGE detector w/ feedback |
!A1 & A2 |
0 |
!A1 |
Logic Modes |
||||
%10000 |
LOGIC never |
0 |
0 |
0 |
%10001 |
LOGIC !A & !B |
!A1 & !B1 |
0 |
0 |
%10010 |
LOGIC A & !B |
A1 & !B1 |
0 |
0 |
%10011 |
LOGIC !B |
!B1 |
0 |
0 |
%10100 |
LOGIC !A & B |
!A1 & B1 |
0 |
0 |
%10101 |
LOGIC !A |
!A1 |
0 |
0 |
%10110 |
LOGIC A <> B |
A1 <> B1 |
0 |
0 |
%10111 |
LOGIC !A | !B |
!A1 | !B1 |
0 |
0 |
%11000 |
LOGIC A & B |
A1 & B1 |
0 |
0 |
%11001 |
LOGIC A == B |
A1 == B1 |
0 |
0 |
%11010 |
LOGIC A |
A1 |
0 |
0 |
%11011 |
LOGIC A | !B |
A1 | !B1 |
0 |
0 |
%11100 |
LOGIC B |
B1 |
0 |
0 |
%11101 |
LOGIC !A | B |
!A1 | B1 |
0 |
0 |
%11110 |
LOGIC A | B |
A1 | B1 |
0 |
0 |
%11111 |
LOGIC always |
1 |
0 |
0 |
*Must set corresponding DIR bit to affect pin A1 = APIN input delayed by 1 clock A2 = APIN input delayed by 2 clocks B1 = BPIN input delayed by 1 clock |
Propeller Help Version 1.1
Copyright © Parallax Inc.
5/13/2009