January 1995 

ADC0831/ADC0832/ADC0834 and ADC0838 
8-Bit Serial I/O A/D Converters with Multiplexer Options 

General Description 

The ADC0831 series are 8-bit successive approximation 
A/D converters with a serial I/O and configurable input multiplexers 
with up to 8 channels. The serial I/O is configured 
to comply with the NSC MICROWIRETM serial data exchange 
standard for easy interface to the COPSTM family of 
processors, and can interface with standard shift registers 
or mPs. 

The 2-, 4-or 8-channel multiplexers are software configured 
for single-ended or differential inputs as well as channel assignment. 


The differential analog voltage input allows increasing the 
common-mode rejection and offsetting the analog zero input 
voltage value. In addition, the voltage reference input 
can be adjusted to allow encoding any smaller analog voltage 
span to the full 8 bits of resolution. 

Features 

Y NSC MICROWIRE compatibleÐdirect interface to 

COPS family processors 
Y Easy interface to all microprocessors, or operates 

``stand-alone'' 

Y 
Operates ratiometrically or with 5 VDC voltage 
reference 

Y No zero or full-scale adjust required 

Y 
2-, 4-or 8-channel multiplexer options with address 
logic 

Y 
Shunt regulator allows operation with high voltage 
supplies 

Y 0V to 5V input range with single 5V power supply 

Y Remote operation with serial digital data link 

Y TTL/MOS input/output compatible 

Y 0.3× standard width, 8-, 14-or 20-pin DIP package 

Y 20 Pin Molded Chip Carrier Package (ADC0838 only) 

Y Surface-Mount Package 

Key Specifications 
Y Resolution 8 Bits 
Y Total Unadjusted Error g(/2 LSB and g1 LSB 
Y Single Supply 5 VDC 
Y Low Power 15 mW 
Y Conversion Time 32 ms 

Typical Application 



ADC0831/ADC0832/ADC0834andADC0838 
8-Bit SerialI/OA/DConverterswith MultiplexerOptions 

TL/H/5583 ± 1 
TRI-STATEÉis a registered trademark of National Semiconductor Corporation. 
COPSTM and MICROWIRETM are trademarks of National Semiconductor Corporation. 
C1995 National Semiconductor Corporation TL/H/5583 RRD-B30M115/Printed in U. S. A. 


Absolute Maximum Ratings (Notes1&2) 
If Military/Aerospace specified devices are required, Lead Temperature (Soldering 10 sec.) 


please contact the National Semiconductor Sales Dual-In-Line Package (Plastic) 260§C 
Office/Distributors for availability and specifications. Dual-In-Line Package (Ceramic) 300§C 
Current intoV a(Note 3) 15 mA 


Molded Chip Carrier Package 
Vapor Phase (60 sec.) 215§C 

Supply Voltage,VCC (Note3) 6.5V 

Infrared (15 sec.) 220§C 

Voltage 

ESD Susceptibility (Note 5) 2000V 

Logic Inputs b0.3V toVCC a0.3V 
Analog Inputs b0.3V toVCC a0.3V 

Operating Ratings (Notes1&2) 

Input Current per Pin (Note 4) g5mA 

Package g20 mA Supply Voltage, VCC 4.5 VDC to 6.3 VDC 
Storage Temperature b65§Cto a150§C Temperature Range TMINsTAsTMAX 
ADC0831/8BCJ, 
Package Dissipation 
at TAe25§C(Board Mount) 0.8W 
ADC0831/4/8CCJ, 
ADC0832BIWM, 
ADC0831/2/4/8CIWM b40§Cto a85§C 
ADC0831/2//4/8BCN, 
ADC0838BCV, 
ADC0831/2/4/8CCN, 
ADC0838CCV, 
ADC0831/2/4/8CCWM 0§Cto a70§C 

Converter and Multiplexer Electrical Characteristics 

The following specifications apply for VCC eVaeVREF e5V, VREF sVCC a0.1V, TA eTj e25§C, and fCLK e250 kHz 
unless otherwise specified. Boldface limits apply from TMIN to TMAX. 

Parameter Conditions 
BCJ, BIWM, 
CIWM and CCJ Devices 
BCV, CCV, CCWM, BCN 
and CCN Devices 
Units 
Typ 
(Note 12) 
Tested 
Limit 
(Note 13) 
Design 
Limit 
(Note 14) 
Typ 
(Note 12) 
Tested 
Limit 
(Note 13) 
Design 
Limit 
(Note 14) 

CONVERTER AND MULTIPLEXER CHARACTERISTICS 

Total Unadjusted Error 
ADC0838BCV 
ADC0831/2/4/8BCN 
ADC0831/8BCJ 
ADC0832BIWM 
ADC0838CCV 
ADC0831/2/4/8CCN 
ADC0831/2/4/8CCWM 
ADC0831/4/8CCJ 
ADC0831/2/4/8CIWM 
VREFe5.00 V 
(Note 6) 
g(/2 
g(/2 
g1 
g1 
g(/2 
g(/2 
g1 
g1 
g1 
g(/2 
g(/2 
g1 
g1 
g1 
LSB 
Minimum Reference 
Input Resistance (Note 7) 
3.5 1.3 3.5 1.3 1.3 kX 
Maximum Reference 
Input Resistance (Note 7) 
3.5 5.9 3.5 5.4 5.9 kX 
Maximum Common-Mode Input 
Range (Note 8) 
VCC a0.05 VCC a0.05 VCCa0.05 V 
Minimum Common-Mode Input 
Range (Note 8) 
GND b0.05 GND b0.05 GNDb0.05 V 
DC Common-Mode Error g(/16 g(/4 g(/16 g(/4 g(/4 LSB 

2 


Converter and Multiplexer Electrical Characteristics (Continued) 
The following specifications apply for VCC e Vae 5V, TA e Tj e 25§C, and fCLK e 250 kHz unless otherwise specified. 


Boldface limits apply from TMIN to TMAX. 

Parameter Conditions 
BCJ, BIWM, 
CIWM and CCJ Devices 
BCV, CCV, CCWM, BCN 
and CCN Devices 
Units 
Typ 
(Note 12) 
Tested 
Limit 
(Note 13) 
Design 
Limit 
(Note 14) 
Typ 
(Note 12) 
Tested 
Limit 
(Note 13) 
Design 
Limit 
(Note 14) 

CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued) 

Change in zero 15 mA into Va 
error from VCCe5V VCCeN.C. 
to internal zener VREFe5V 
operation (Note 3) 1 1 1 LSB 
VZ, internal MIN 15 mA into Va 6.3 6.3 6.3 
diode breakdown MAX 8.5 8.5 8.5 V 
(at Va)(Note 3) 
Power Supply Sensitivity VCCe5Vg5% g(/16 g(/4 g(/4 g(/16 g(/4 g(/4 LSB 
IOFF, Off Channel Leakage On Channele5V, b0.2 b0.2 b1 mA 
Current (Note 9) Off Channele0V b1 
On Channele0V, 
Off Channele5V 
a0.2 
a1 
a0.2 a1 mA 
ION,On Channel Leakage On Channele0V, b0.2 b0.2 b1 mA 
Current (Note 9) Off Channele5V b1 
On Channele5V, 
Off Channele0V 
a0.2 
a1 
a0.2 a1 mA 
DIGITAL AND DC CHARACTERISTICS 
VIN(1),Logical ``1'' Input 
Voltage (Min) 
VCCe5.25V 2.0 2.0 2.0 V 
VIN(0),Logical ``0'' Input 
Voltage (Max) 
VCCe4.75V 0.8 0.8 0.8 V 
IIN(1), Logical ``1'' Input 
Current (Max) 
VINe5.0V 0.005 1 0.005 1 1 mA 
IIN(0), Logical ``0'' Input 
Current (Max) 
VINe0V b0.005 b1 b0.005 b1 b1 mA 
VOUT(1),Logical ``1'' Output VCCe4.75V 
Voltage (Min) IOUTeb360 mA 2.4 2.4 2.4 V 
IOUTeb10 mA 4.5 4.5 4.5 V 
VOUT(0),Logical ``0'' Output 
Voltage (Max) 
VCCe4.75V 
IOUTe1.6 mA 
0.4 0.4 0.4 V 
IOUT,TRI-STATE Output VOUTe0V b0.1 b3 b0.1 b3 b3 mA 
Current (Max) VOUTe5V 0.1 3 0.1 a3 a3 mA 
ISOURCE,Output Source 
Current (Min) 
VOUTe0V b14 b6.5 b14 b7.5 b6.5 mA 
ISINK, Output Sink Current (Min) VOUTeVCC 16 8.0 16 9.0 8.0 mA 
ICC,Supply Current (Max) 
ADC0831, ADC0834, 0.9 2.5 0.9 2.5 2.5 mA 
ADC0838 
ADC0832 Includes Ladder 
Current 
2.3 6.5 2.3 6.5 6.5 mA 

3 


AC Characteristics 

The following specifications apply for VCC e 5V, tr e tf e 20 ns and25§C unless otherwise specified. 

Parameter Conditions 
Typ 
(Note 12) 
Tested 
Limit 
(Note 13) 
Design 
Limit 
(Note 14) 
Limit 
Units 
fCLK, Clock Frequency 
Min 
Max 
10 
400 
kHz 
kHz 
tC,Conversion Time Not including MUX Addressing Time 8 1/fCLK 
Clock Duty Cycle 
(Note 10) 
Min 
Max 
40 
60 
% 
% 
tSET-UP,CS Falling Edge or 
Data Input Valid to CLK 
Rising Edge 
250 ns 
tHOLD, Data Input Valid 
after CLK Rising Edge 
90 ns 
tpd1,tpd0ÐCLK Falling 
Edge to Output Data Valid 
(Note 11) 
CLe100 pF 
Data MSB First 
Data LSB First 
650 
250 
1500 
600 
ns 
ns 
t1H,t0H,ÐRising Edge of 
CS to Data Output and 
CLe10 pF, RLe10k 
(see TRI-STATEÉTest Circuits) 
125 250 ns 
SARS Hi ± Z 
CLe100 pf, RLe2k 500 ns 
CIN, Capacitance of Logic 
Input 
5 pF 
COUT, Capacitance of Logic 
Outputs 
5 pF 

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating 
the device beyond its specified operating conditions. 

Note 2: All voltages are measured with respect to the ground plugs. 
Note 3: Internal zener diodes (6.3 to 8.5V) are connected fromV a to GND and VCC to GND. The zener at Va can operate as a shunt regulator and is connected 
toVCC viaa conventional diode. Since the zener voltage equalsthe A/D's breakdown voltage, the diode insures thatVCC willbe below breakdown when the device 
is powered from Va. Functionality is therefore guaranteed for Va operation even though the resultant voltage at VCC may exceed the specified Absolute Max of 
6.5V. It is recommended that a resistor be used to limit the max current into Va. (SeeFigure 3 in Functional Description Section 6.0) 

Note 4: When the input voltage (VIN)at any pin exceeds the power supply rails (VIN k Vb or VIN l Va)the absolute value of current at that pin should be limited 
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries witha5mA current limit to four. 
Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor. 
Note 6: Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors. 

Note 7: Cannot be tested for ADC0832. 
Note 8: For VIN(b)tVIN(a)the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward 
conduct for analog input voltages one diode drop below ground or one diode drop greater then the VCC supply. Be careful, during testing at low VCC levels (4.5V), 
as high level analog inputs (5V) can cause this input diode to conductÐespecially at elevated temperatures, and cause errors for analog inputs near full-scale. The 
spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 50 mV, the 
output code will be correct. To achieve an absolute 0 VDC to5VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over 
temperature variations, initial tolerance and loading. 

Note 9: Leakage current is measured with the clock not switching. 
Note 10: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of 

these limits, the minimum, time the clock is high or the minimum time the clock is low must be at least1 ms. The maximum time the clock can be high is 60 ms. The 
clock can be stopped when low so long as the analog input voltage remains stable. 
Note 11: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to 

allow for comparator response time. 
Note 12: Typicals are at 25§C and represent most likely parametric norm. 
Note 13: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level). 
Note 14: Guaranteed but not 100% production tested. These limits are not used to calculate outgoing quality levels. 

4 


Typical Performance Characteristics 


Unadjusted Offset Error Linearity Error vsVREF Linearity Error vs 
vsVREF Voltage Voltage Temperature 


TL/H/5583 ± 2 
Power Supply Current vs 
Temperature (ADC0838, Output Current vs 
Linearity Error vs fCLK ADC0831, ADC0834) Temperature 


Note: For ADC0832 addIREF. TL/H/5583 ±40 

Power Supply Current 
vsfCLK 


Leakage Current Test Circuit 

TL/H/5583 ±29 

TL/H/5583 ±3 


5 


TRI-STATE Test Circuits and Waveforms 


t1H t1H 

t0H 
t0H 
TL/H/5583 ±4 TL/H/5583 ±23 

Timing Diagrams 

Data Input Timing Data Output Timing 


TL/H/5583 ±24 

TL/H/5583 ±25 

ADC0831 Start Conversion Timing 


TL/H/5583 ±26 

6 


Timing Diagrams (Continued) 

ADC0831 Timing 


TL/H/5583 ±27 

*LSB first output not available on ADC0831. 

ADC0832 Timing 


TL/H/5583 ±28 

ADC0834 Timing 


TL/H/5583 ±5 

7 


Timing Diagrams (Continued) 
ADC0838Timing 
TL/H/5583±6 
* Make sure clock edge Ý18 clocks in the LSB before SE is taken low 
TL/H/5583±6 
* Make sure clock edge Ý18 clocks in the LSB before SE is taken low 
8 


ADC0838 Functional Block Diagram 
TL/H/5583±7 
*Some of these functions/pins are not available with other options. 
Note 1: For the ADC0834, D1 is input directly to the D input of SELECT 1. SELECT 0 is forced to a ``1''. For the ADC0832, DI is input directly to the DI input of 
ODD/SIGN. SELECT 0 is forced to a ``0'' and SELECT 1 is forced to a ``1''. 
TL/H/5583±7 
*Some of these functions/pins are not available with other options. 
Note 1: For the ADC0834, D1 is input directly to the D input of SELECT 1. SELECT 0 is forced to a ``1''. For the ADC0832, DI is input directly to the DI input of 
ODD/SIGN. SELECT 0 is forced to a ``0'' and SELECT 1 is forced to a ``1''. 
9 


Connection Diagrams 


ADC0838 8-Channel MUX ADC0834 4-Channel MUX 
Small Outline/Dual-In-Line Package(J,MandN) Small Outline/Dual-In-Line Package(J,M,andN) 



TL/H/5583 ±30 

Top View 

COM internally connected toAGND 

TL/H/5583 ±31 

Top View 

COM internally connected to GND. 
VREF internally connected to VCC. 


TL/H/5583 ±8 

Top View 

ADC0832 2-Channel MUX ADC0832 2-Channel MUX ADC0831 Single 
Differential Input 


Dual-In-Line Package (J and N) Small Outline Package (M) 
Dual-In-Line Package (J and N) 

ADC0831 Single Differential Input ADC0838 8-Channel MUX 
Small Outline Package (M) Molded Chip Carrier (PCC) Package (V) 

TL/H/5583 ±41 

Top View 


TL/H/5583 ±32 

Top View 


TL/H/5583 ±42 

Top View 


10 

TL/H/5583 ±33 


Functional Description 

1.0 MULTIPLEXER ADDRESSING 

The design of these converters utilizes a sample-data com-tial. In the differential case, it also assigns the polarity of the 
parator structure which provides for a differential analog in-channels. Differential inputs are restricted to adjacent chanput 
to be converted by a successive approximation routine. nel pairs. For example channel 0 and channel 1 may be 

The actual voltage converted is always the difference be-

selected as a different pair but channel 0 or 1 cannot act 
tween an assigned `` a'' input terminal and a ``b'' input ter


differentially with any other channel. In addition to selecting 
minal. The polarity of each input terminal of the pair being 

differential mode the sign may also be selected. Channel 0 
converted indicates which line the converter expects to be 

may be selected as the positive input and channel 1 as the 
the most positive. If the assigned `` a'' input is less than the 

negative input or vice versa. This programmability is best 
``b'' input the converter responds with an all zeros output 

illustrated by the MUX addressing codes shown in the folcode. 


lowing tables for the various product options. 
A unique input multiplexing scheme has been utilized to pro-

The MUX address is shifted into the converter via the DI 
vide multiple analog channels with software-configurable 

line. Because the ADC0831 contains only one differential 
single-ended, differential, or a new pseudo-differential op


input channel with a fixed polarity assignment, it does not 
tion which will convert the difference between the voltage at 

require addressing. 
any analog input and a common terminal. The analog signal The common input line on the ADC0838 can be used as a 
conditioning required in transducer-based data acquisition pseudo-differential input. In this mode, the voltage on this 
systems is significantly simplified with this type of input flexi-pin is treated as the ``b'' input for any of the other input 
bility. One converter package can now handle ground refer-channels. This voltage does not have to be analog ground; 

enced inputs and true differential inputs as well as signals it can be any reference potential which is common to all of 
with some arbitrary reference voltage. the inputs. This feature is most useful in single-supply appli-
A particular input configuration is assigned during the MUX 

cation where the analog circuitry may be biased up to a 
addressing sequence, prior to the start of a conversion. The 

potential other than ground and the output signals are all 
MUX address selects which of the analog inputs are to be 

referred to this potential. 
enabled and whether this input is single-ended or differen-

TABLE I. Multiplexer/Package Options 

Part Number of Analog Channels Number of 
Package Pins Number 
Single-Ended Differential 
ADC0831 1 1 8 
ADC0832 2 1 8 
ADC0834 4 2 14 
ADC0838 8 4 20 

11 


Functional Description (Continued) 

TABLE II. MUX Addressing: ADC0838 

Single-Ended MUX Mode 

MUX Address Analog Single-Ended Channel Ý 
SGL/ 
DIF 
ODD/ 
SIGN 
SELECT 
1 0 
0 1 2 3 4 5 6 7 COM 
1 0 0 0 a b 
1 0 0 1 a b 
1 0 1 0 a b 
1 0 1 1 a b 
1 1 0 0 a b 
1 1 0 1 a b 
1 1 1 0 a b 
1 1 1 1 a b 

Differential MUX Mode 

MUX Address Analog Differential Channel-Pair Ý 
SGL/ 
DIF 
ODD/ 
SIGN 
SELECT 0 1 2 3 
1 0 0 1 2 3 4 5 6 7 
0 0 0 0 a b 
0 0 0 1 a b 
0 0 1 0 a b 
0 0 1 1 a b 
0 1 0 0 b a 
0 1 0 1 b a 
0 1 1 0 b a 
0 1 1 1 b a 

TABLE III. MUX Addressing: ADC0834 TABLE IV. MUX Addressing: 
Single-Ended MUX Mode ADC0832 

MUX Address Channel Ý 
SGL/ 
DIF 
ODD/ 
SIGN 
SELECT 
0 1 2 31 
1 0 0 a 
1 0 1 a 
1 1 0 a 
1 1 1 a 

Single-Ended MUX Mode 

MUX Address Channel Ý 
SGL/ 
DIF 
ODD/ 
SIGN 
0 1 
1 0 a 
1 1 a 

COM is internally tied toAGND 

COM is internally tied toA GND 

Differential MUX Mode 

Differential MUX Mode 

MUX Address Channel Ý 
SGL/ 
DIF 
ODD/ 
SIGN 
SELECT 
0 1 2 31 
0 0 0 a b 
0 0 1 a b 
0 1 0 b a 
0 1 1 b a 

MUX Address Channel Ý 
SGL/ 
DIF 
ODD/ 
SIGN 
0 1 
0 0 a b 
0 1 b a 

12 


Functional Description (Continued) 
Since the input configuration is under software control, it 
can be modified, as required, at each conversion.A channel 
can be treated as a single-ended, ground referenced input 
for one conversion; then it can be reconfigured as part of a 

differential channel for another conversion. Figure 1 illustrates 
the input flexibility which can be achieved. 
The analog input voltages for each channel can range from 

50 mV below ground to 50 mV above VCC (typically 5V) 
without degrading conversion accuracy. 

2.0 THE DIGITAL INTERFACE 

A most important characteristic of these converters is their 
serial data link with the controlling processor. Using a serial 
communication format offers two very significant system improvements; 
it allows more function to be included in the 
converter package with no increase in package size and it 
can eliminate the transmission of low level analog signals by 
locating the converter right at the analog sensor; transmitting 
highly noise immune digital data back to the host processor. 


8 Single-Ended 

4 Differential 

To understand the operation of these converters it is best to 
refer to the Timing Diagrams and Functional Block Diagram 
and to follow a complete conversion sequence. For clarity a 
separate diagram is shown of each device. 

1. A conversion is initiated by first pulling the CS (chip select) 
line low. This line must be held low for the entire conversion. 
The converter is now waiting for a start bit and its 
MUX assignment word. 

2. A clock is then generated by the processor (if not provid


ed continuously) and output to the A/D clock input. 
3. On each rising edge of the clock the status of the data in 
(DI) line is clocked into the MUX address shift register. The 
start bit is the first logic ``1'' that appears on this line (all 
leading zeros are ignored). Following the start bit the converter 
expects the next 2 to 4 bits to be the MUX assignment 
word. 

8 Pseudo-Differential 

Mixed Mode 


TL/H/5583 ±9 

FIGURE 1. Analog Input Multiplexer Options for the ADC0838 

13 


Functional Description (Continued) 
4. When the start bit has been shifted into the start location 
of the MUX register, the input channel has been assigned 
and a conversion is about to begin. An interval of (/2 clock 
period (where nothing happens) is automatically inserted to 
allow the selected MUX channel to settle. The SAR status 
line goes high at this time to signal that a conversion is now 

in progress and the DI line is disabled (it no longer accepts 
data). 
5. The data out (DO) line now comes out of TRI-STATE and 

provides a leading zero for this one clock period of MUX 

settling time. 
6. When the conversion begins, the output of the SAR comparator, 
which indicates whether the analog input is greater 
than (high) or less than (low) each successive voltage from 
the internal resistor ladder, appears at the DO line on each 
falling edge of the clock. This data is the result of the conversion 
being shifted out (with the MSB coming first) and 
can be read by the processor immediately. 

7. After 8 clock periods the conversion is completed. The 
SAR status line returns low to indicate this (/2 clock cycle 
later. 

8. If the programmer prefers, the data can be provided in an 
LSB first format [this makes use of the shift enable (SE) 
control line]. All 8 bits of the result are stored in an output 
shift register. On devices which do not include the SE control 
line, the data, LSB first, is automatically shifted out the 
DO line, after the MSB first data stream. The DO line then 
goes low and stays low until CS is returned high. On the 
ADC0838 the SE line is brought out and if held high, the 
value of the LSB remains valid on the DO line. When SE is 
forced low, the data is then clocked out LSB first. The 
ADC0831 is an exception in that its data is only output in 
MSB first format. 

9. All internal registers are cleared when the CS line is high. 
If another conversion is desired, CS must make a high to 
low transition followed by address information. 

The DI and DO lines can be tied together and controlled 
through a bidirectional processor I/O bit with one wire. This 
is possible because the DI input is only ``looked-at'' during 
the MUX addressing interval while the DO line is still in a 
high impedance state. 

3.0 REFERENCE CONSIDERATIONS 

The voltage applied to the reference input to these converters 
defines the voltage span of the analog input (the difference 
between over which the 256 

VIN(MAX) and VIN(MIN)) 
possible output codes apply. The devices can be used in 
either ratiometric applications or in systems requiring absolute 
accuracy. The reference pin must be connected to a 
voltage source capable of driving the reference input resistance 
of typically 3.5 kX. This pin is the top of a resistor 
divider string used for the successive approximation conversion. 


In a ratiometric system, the analog input voltage is proportional 
to the voltage used for the A/D reference. This voltage 
is typically the system power supply, so the VREF pin 
can be tied to VCC (done internally on the ADC0832). This 
technique relaxes the stability requirements of the system 
reference as the analog input and A/D reference move together 
maintaining the same output code for a given input 
condition. 

For absolute accuracy, where the analog input varies between 
very specific voltage limits, the reference pin can be 
biased with a time and temperature stable voltage source. 
The LM385 and LM336 reference diodes are good low current 
devices to use with these converters. 

The maximum value of the reference is limited to the VCC 
supply voltage. The minimum value, however, can be quite 
small (see Typical Performance Characteristics) to allow direct 
conversions of transducer outputs providing less than a 
5V output span. Particular care must be taken with regard to 
noise pickup, circuit layout and system error voltage sources 
when operating with a reduced span due to the increased 
sensitivity of the converter (1 LSB equals VREF/ 
256). 


TL/H/5583 ±10 

a) Ratiometric b) Absolute with a Reduced Span 
FIGURE 2. Reference Examples 

14 


Functional Description (Continued) 

4.0 THE ANALOG INPUTS 5.2 Full-Scale 

The most important feature of these converters is that they The full-scale adjustment can be made by applying a differ-
can be located right at the analog signal source and through ential input voltage which is1 (/2 LSB down from the desired 
just a few wires can communicate with a controlling proces-analog full-scale voltage range and then adjusting the magsor 
with a highly noise immune serial bit stream. This in itself nitude of the VREF input (or VCC for the ADC0832) for a 
greatly minimizes circuitry to maintain analog signal accura-digital output code which is just changing from 1111 1110 to 
cy which otherwise is most susceptible to noise pickup. 1111 1111. 
However, a few words are in order with regard to the analog 

5.3 Adjusting for an Arbitrary Analog Input Voltage 

inputs should the input be noisy to begin with or possibly 

Range

riding on a large common-mode voltage. 
If the analog zero voltage of the A/D is shifted away from 

The differential input of these converters actually reduces 

ground (for example, to accommodate an analog input sig


the effects of common-mode input noise, a signal common 

nal which does not go to ground), this new zero reference 

to both selected `` a'' and ``b'' inputs for a conversion (60 

should be properly adjusted first. AVIN(a) voltage which 

Hz is most typical). The time interval between sampling the 

.J 
#J 
equals this desired zero reference plus (/2 LSB (where the 

`` a'' input and then the ``b'' input is (/2 of a clock period. 

LSB is calculated for the desired analog span, using

The change in the common-mode voltage during this short 

1 LSBe analog span/256) is applied to selected `` a'' input

time interval can cause conversion errors. For a sinusoidal 

and the zero reference voltage at the corresponding ``b'' 

common-mode signal this error is: 

input should then be adjusted to just obtain the 00HEX to 

0.5 Ð(

01HEX code transition. 

(max)e VPEAK(2qfCM)

Verror

fCLK The full-scale adjustment should be made [with the proper 
where fCM is the frequency of the common-mode signal, VIN(b) voltage applied] by forcing a voltage to the VIN(a) 

input which is given by: 

VPEAK is its peak voltage value 

and fCLK, is the A/D clock frequency. (VMAXbVMIN)

VIN(a)fsadj e VMAXb1.5 
For a 60 Hz common-mode signal to generate a (/4 LSB 

256 
error (&5 mV) with the converter running at 250 kHz, its where: 
peak value would have to be 6.63V which would be larger 

e the high end of the analog input range 
than allowed as it exceeds the maximum analog input limits. 

VMAX 

and 
Due to the sampling nature of the analog inputs short spikes 

VMIN e the low end (the offset zero) of the analog

of current enter the `` a'' input and exit the ``b'' input at the 

range.

clock edges during the actual conversion. These currents 
decay rapidly and do not cause errors as the internal com


(Both are ground referenced.) 

parator is strobed at the end of a clock period. Bypass ca-The VREF (or VCC) voltage is then adjusted to provide a 
pacitors at the inputs will average these currents and cause code change from FEHEX to FFHEX. This completes the ad-
an effective DC current to flow through the output resist-justment procedure. 
ance of the analog signal source. Bypass capacitors should 

6.0 POWER SUPPLY 

not be used if the source resistance is greater than 1 kX. 
A unique feature of the ADC0838 and ADC0834 is the inclu-

This source resistance limitation is important with regard to 

sion of a zener diode connected from the Va terminal to 

the DC leakage currents of input multiplexer as well. The 

ground which also connects to the VCC terminal (which is 

worst-case leakage current of g1 mA over temperature will 

the actual converter supply) through a silicon diode, as 

createa1mV input error witha1kX source resistance. An 

shown in Figure 3 . (See Note 3) 

op amp RC active low pass filter can provide both impedance 
buffering and noise filtering should a high impedance 
signal source be required. 

5.0 OPTIONAL ADJUSTMENTS 

5.1 Zero Error 

The zero of the A/D does not require adjustment. If the 
minimum analog input voltage value, VIN(MIN), is not ground 
a zero offset can be done. The converter can be made to 
output 0000 0000 digital code for this minimum input voltage 
by biasing any VIN (b) input at this VIN(MIN) value. This 
utilizes the differential mode operation of the A/D. 

The zero error of the A/D converter relates to the location 
of the first riser of the transfer function and can be measured 
by grounding the VIN(b) input and applying a small 

TL/H/5583 ±11 

magnitude positive voltage to theVIN(a)input. Zero error is 

FIGURE 3. An On-Chip Shunt Regulator Diode 

the difference between the actual DC input voltage which is 
necessary to just cause an output digital code transition 
from 0000 0000 to 0000 0001 and the ideal (/2 LSB value 
((/2 LSBe9.8 mV for VREFe5.000 VDC). 


15 


TL/H/5583 ±12 

FIGURE 4. Operating with a Temperature 
Compensated Reference 


TL/H/5583 ±34 

FIGURE 5. Using the A/D as 
the System Supply Regulator 


*Note: 4.5V s VCC s 6.3V 

TL/H/5583 ±35 

FIGURE 6. GeneratingVCC from the Converter Clock 

TL/H/5583 ±36 

FIGURE 7. Remote SensingÐ 
Clock and Power on1Wire 

16 

Functional Description (Continued) 
This zener is intended for use as a shunt voltage regulator 
to eliminate the need for any additional regulating components. 
This is most desirable if the converter is to be remotely 
located from the system power source. Figures 4 

and 5 illustrate two useful applications of this on-board zener 
when an external transistor can be afforded. 
An important use of the interconnecting diode between Va 

and VCC is shown in Figures 6 and 7. Here, this diode is 
used as a rectifier to allow the VCC supply for the converter 

Applications 


to be derived from the clock. The low current requirements 
of the A/D and the relatively high clock frequencies used 
(typically in the range of 10k±400 kHz) allows using the 
small value filter capacitor shown to keep the ripple on the 
VCC line to well under (/4 of an LSB. The shunt zener regulator 
can also be used in this mode. This requires a clock 
voltage swing which is in excess ofVZ.A current limit for the 
zener is needed, either built into the clock generator or a 
resistor can be used from the CLK pin to the Va pin. 


Applications (Continued) 

Digital Link and Sample Controlling Software for the 
Serially Oriented COP420 and the Bit Programmable I/O INS8048 


COP CODING EXAMPLE 

Mnemonic Instruction 
LEI ENABLES SIO's INPUT AND OUTPUT 
SC C e 1 
OGI G0e0(CSe0) 
CLR A CLEARS ACCUMULATOR 
AISC 1 LOADS ACCUMULATOR WITH 1 
XAS EXCHANGES SIO WITH ACCUMULATOR 
AND STARTS SK CLOCK 
LDD LOADS MUX ADDRESS FROM RAM 
INTO ACCUMULATOR 
NOP Ð 
XAS LOADS MUX ADDRESS FROM 
ACCUMULATOR TO SIO REGISTER 
u 

8 INSTRUCTIONS 

v 

XAS READS HIGH ORDER NIBBLE (4 BITS) 

INTO ACCUMULATOR 
XIS PUTS HIGH ORDER NIBBLE INTO RAM 
CLRA CLEARS ACCUMULATOR 
RC C e 0 
XAS READS LOW ORDER NIBBLE INTO 

ACCUMULATOR AND STOPS SK 
XIS PUTS LOW ORDER NIBBLE INTO RAM 
OGI G0e1(CSe1) 
LEI DISABLES SIO's INPUT AND OUTPUT 

8048 CODING EXAMPLE 
Mnemonic 

START: ANL P1, Ý0F7H 
MOV B, Ý5 
MOV A, ÝADDR 
LOOP 1: RRC A 
JC ONE 
ZERO: ANL P1, Ý0FEH 
JMP CONT 
ONE: ORL P1, Ý1 
CONT: CALL PULSE 
DJNZ B, LOOP 1 
CALL PULSE 
MOV B, Ý8 
LOOP 2: CALL PULSE 
IN A, P1 
RRC A 
RRC A 
MOV A, C 
RLC A 
MOV C, A 
DJNZ B, LOOP 2 
RETR 
PULSE: ORL P1, Ý04 
NOP 
ANL P1, Ý0FBH 
RET 

TL/H/5583 ±13 

Instruction 

;SELECT A/D (CS e0) 

;BIT COUNTERw5 
;AwMUX ADDRESS 
;CYwADDRESS BIT 
;TEST BIT 
;BITe0 
;DIw0 
;CONTINUE 
;BITe1 
;DIw1 
;PULSE SK0 x1x0 
;CONTINUE UNTIL DONE 
;EXTRA CLOCK FOR SYNC 
;BIT COUNTERw8 
;PULSE SK0 x1x0 
;CYwDO 
;AwRESULT 
;A(0)wBIT AND SHIFT 
;CwRESULT 
;CONTINUE UNTIL DONE 
;PULSE SUBROUTINE 
;SKw1 
;DELAY 
;SKw0 
17 


Applications (Continued) 

A ``Stand-Alone'' Hook-Up for ADC0838 Evaluation 

*Pinouts shown for ADC0838. 
For all other products tie to 
pin functions as shown. 


Low-Cost Remote Temperature Sensor 

TL/H/5583 ±14 

18 


Applications (Continued) 

Digitizing a Current Flow 


TL/H/5583 ±15 

Operating with Ratiometric Transducers 


TL/H/5583 ±37 

*VIN(b) e 0.15 VCC 
15% of VCC s VXDR s 85% of VCC 

19 


Applications (Continued) 

Span Adjust: OVsVINs3V 

Zero-Shift and Span Adjust: 2V sVINs5V 


TL/H/5583 ±16 

20 


Applications (Continued) 

Obtaining Higher Resolution 


TL/H/5583 ±17 
Controller performs a routine to determine which input polarity (9-bit example) or which channel pair (10-bit example) provides a non-zero output code. 
This information provides the extra bits. 

a) 9-Bit A/D b)10-Bit A/D 
Protecting the Input 

Diodes are 1N914 

TL/H/5583 ±18 

21 


Applications (Continued) 

High Accuracy Comparators 

DO e all 1s if aVIN lbVIN 
DO e all 0s if aVIN kbVIN 
TL/H/5583 ±38 

Digital Load Cell 


TL/H/5583 ±19 

# Uses one more wire than load cell itself 
# Two mini-DIPs could be mounted inside load cell for digital output transducer 
# Electronic offset and gain trims relax mechanical specs for gauge factor and offset 
# Low level cell output is converted immediately for high noise immunity 
22 


Applications (Continued) 

4mA±20 mACurrent Loop Converter 

# All power supplied by loop 
# 1500V isolation at output TL/H/5583 ± 20 
Isolated Data Converter 

#No power required remotely 
#1500V isolation 
TL/H/5583 ±39 

23 


Applications (Continued) 
TL/H/5583 ± 21 
TwoWire Interface for 8Channels 
TL/H/5583 ± 21 
TwoWire Interface for 8Channels 
24 


Applications (Continued) 
Two Wire 1-Channel Interface 
TL/H/5583 ± 22 
Ordering Information 
Part Number 
Analog Input Total 
Package 
Temperature 
Channels Unadjusted Error Range 
ADC0831BCJ 
1 
g(/2 
Hermetic (J) b40§Cto a85§C 
ADC0831BCN Molded (N) 0§Cto a70§C 
ADC0831CCJ 
g1 
Hermetic (J) b40§Cto a85§C 
ADC0831CCN Molded (N) 0§Cto a70§C 
ADC0831CIWM SO(M) b40§Cto a85§C 
ADC0831CCWM SO(M) 0§Cto a70§C 
ADC0832BIWM 
2 
g(/2 
SO(M) b40§Cto a85§C 
ADC0832BCN Molded (N) 0§Cto a70§C 
ADC0832CIWM 
g1 
SO(M) b40§Cto a85§C 
ADC0832CCN Molded (N) 0§Cto a70§C 
ADC0832CCWM SO(M) 0§Cto a70§C 
TL/H/5583 ± 22 
Ordering Information 
Part Number 
Analog Input Total 
Package 
Temperature 
Channels Unadjusted Error Range 
ADC0831BCJ 
1 
g(/2 
Hermetic (J) b40§Cto a85§C 
ADC0831BCN Molded (N) 0§Cto a70§C 
ADC0831CCJ 
g1 
Hermetic (J) b40§Cto a85§C 
ADC0831CCN Molded (N) 0§Cto a70§C 
ADC0831CIWM SO(M) b40§Cto a85§C 
ADC0831CCWM SO(M) 0§Cto a70§C 
ADC0832BIWM 
2 
g(/2 
SO(M) b40§Cto a85§C 
ADC0832BCN Molded (N) 0§Cto a70§C 
ADC0832CIWM 
g1 
SO(M) b40§Cto a85§C 
ADC0832CCN Molded (N) 0§Cto a70§C 
ADC0832CCWM SO(M) 0§Cto a70§C 
25 


Ordering Information (Continued) 

Analog Input Total TemperaturePart Number PackageChannels Unadjusted Error Range 
ADC0834BCN g(/2 Molded (N) 0§Cto a70§C 
ADC0834CCJ Hermetic (J) b40§Cto a85§C 
ADC0834CCN 4 
g1 Molded (N) 0§Cto a70§C 
ADC0834CCWM SO(M) 0§Cto a70§C 
ADC0834CIWM SO(M) b40§Cto a85§C 
ADC0838BCJ Hermetic (J) b40§Cto a85§C 
ADC0838BCV g(/2 
PCC (V) 0§Cto a70§C 
ADC0838BCN Molded (N) 0§Cto a70§C 
ADC0838CCJ 8 Hermetic (J) b40§Cto a85§C 
ADC0838CCV PCC (V) 0§Cto a70§C 
ADC0838CCN g1 Molded (N) 0§Cto a70§C 
ADC0838CIWM SO(M) b40§Cto a85§C 
ADC0838CCWM SO(M) 0§Cto a70§C 

See NS Package Number J08A, J14A, J20A, M14B, M20B, N08E, N14A, N20A or V20A 

26 


27 


Physical Dimensions inches (millimeters) 
Ceramic Dual-In-Line Package (J) 
NS Package Number J08A 
Ceramic Dual-In-Line Package (J) 
NS Package Number J14A 
Ceramic Dual-In-Line Package (J) 
NS Package Number J08A 
Ceramic Dual-In-Line Package (J) 
NS Package Number J14A 
28 


Physical Dimensions inches (millimeters) (Continued) 
Ceramic Dual-In-Line Package (J) 
NS Package Number J20A 
Hermetic Dual-In-Line Package (M) 
NS Package Number M14B 
Ceramic Dual-In-Line Package (J) 
NS Package Number J20A 
Hermetic Dual-In-Line Package (M) 
NS Package Number M14B 
29 


Physical Dimensions inches (millimeters) (Continued) 
Hermetic Dual-In-Line Package (M) 
NS Package Number M20B 
Molded Dual-In-Line Package (N) 
NS Package Number N08E 
Hermetic Dual-In-Line Package (M) 
NS Package Number M20B 
Molded Dual-In-Line Package (N) 
NS Package Number N08E 
30 


Physical Dimensions inches (millimeters) (Continued) 
Molded Dual-In-Line Package (N) 
NS Package Number N14A 
Molded-Dual-In-Line Package (N) 
NS Package Number N20A 
Molded Dual-In-Line Package (N) 
NS Package Number N14A 
Molded-Dual-In-Line Package (N) 
NS Package Number N20A 
31 


ADC0831/ADC0832/ADC0834andADC08388-Bit SerialI/OA/DConverterswith MultiplexerOptions

Physical Dimensions inches (millimeters) (Continued) 


Molded Chip Carrier Package (V) 
Order Number ADC0838BCV or ADC0838CCV 
NS Package Number V20A 


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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL 
SEMICONDUCTOR CORPORATION. As used herein: 

1. Life support devices or systems are devices or 2. A critical component is any component of a life 
systems which, (a) are intended for surgical implant support device or system whose failure to perform can 
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life 
failure to perform, when properly used in accordance support device or system, or to affect its safety or 
with instructions for use provided in the labeling, can effectiveness. 
be reasonably expected to result in a significant injury 
to the user. 


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Corporation Europe Hong Kong Ltd. Japan Ltd. 

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. 


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