The LCD is 200 rows by 640 columns

The LCD is organized in two parts: 64 rows by 320 sets of 4 pixels, and another 36 by 320 sets of 4 pixels
The first part comprises rows 0-63 and 100-163, with row 0 wrapping around to 100, and so on.
The second part comprises rows 64-99 and 164-199, with row 64 wrapping around to 164.

The use of the word "row" above means physical rows. There are virtual rows that you shift bits into,
which are 1280 pixels wide. The first such virtual row makes up physical row 0, then at the end of
the physical row, goes to row 100 and to its end. The second virtual row is shown with the arrows below.

      rows 0-63 controlled by one 1180
      _______________|_______________
     /                               \
     0   1   2        12  13  14  15       153 153 154 155 156 157 158 159  <-- 4 bit sets
     012301230123 ... 0123012301230123 ... 01230123012301230123012301230123 <-- actual pixels in 4 bit sets
     _____________________________________________________________________
0   |                                                                     | \
1   |  -->   -->   -->   -->   -->   -->   -->   -->   -->   -->   -->    | |
2   |                                                                     | |
.   |                                                                     | +- driven by 1192 (same as 1190)
.   |                                                                     | |
62  |                                                                     | |
63  |_____________________________________________________________________| /
64  |                                                                     | \
65  |                                                                     | |
.   |                                                                     | |
.   |                                                                     | +- driven by 1190
98  |                                                                     | |
99  |_____________________________________________________________________| /
100 |                                                                     |
101 |  -->   -->   -->   -->   -->   -->   -->   -->   -->   -->   -->    |
.   |                                                                     |
.   |                                                                     |
162 |                                                                     |
163 |_____________________________________________________________________|
164 |                                                                     |
165 |                                                                     |
.   |                                                                     |
.   |                                                                     |
198 |                                                                     |
199 |_____________________________________________________________________|

There are 20 SED1180 chips that drive each virtual row.
There is a SED1190 and SED1192 (basically a SED1190) that drive the
rows in each half.

 1 D0 \
 2 D1 |_ D[3..0]   (4 consecutive pixels on a row)
 3 D2 |
 4 D3 /
 5 Display enable  (drive high to turn on LCD)
 6 AC Drive signal (FR on 1180 and 1190, toggles every frame (on a DI pulse))
 7 Y Shift Clock   (LAT on 1190, pulses once per row, falling edge latches DI)
 8 LCD sense       (output, pulls low to signal presence of LCD connection)
 9 X Enable clock  (ECL on 1180, pulsed every 16 XSCL)
10 X Shift clock   (XSCL on 1180, pulse ever pixel, falling edge latches data)
11 VDD             (+5 volts)
12 GND
13 GND
14 Start Frame     (DI on 1190, pulse once per frame (every 100 LP's))
15 GND
16 VEE             (as negative as -13 volts)
17 GND
18 Latch Pulse     (LP on 1180 and YSCL on 1190, pulse once per row (320 XSCL's), can make same as LAT)
19 Reserved        (N.C.)
20 Reserved        (N.C.)

- Victor Liu
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