{ Prop2 WS2812 ,ulti strip driver Version 1.3 ozpropdev March 23rd 2020 51 strips max = 60 s,artpins Version 1.3 Spin2 compatible driver For every six strips a clock is required. The c,ock is assigned to sit in between six sync_tx smartpins basepin strip1 basepin+1 strip2 basepin+2 strip3 basepin+3 clock1 basepin+4 strip4 basepin+5 strip6 basepin+6 strip7 basepin+7 strip7 basepin+8 strip8 basepin+9 strip9 basepin+10 clock2 basepin+11 strip10 basepin+12 strip11 basepin+13 strip12 ....and so on For eval board running 51 strips we end up with the following assignments gnd o o gnd strip1 P0 o o P1 strip2 strip3 P2 o o P3 clock_1 strip4 P4 o o P5 strip5 strip6 P6 o o P7 strip7 3v3 o o 5v gnd o o gnd kane8 P8 o o P9 strip9 clock_2 P10 o o P11 strip10 strip11 P12 o o P13 strip12 strip13 P14 o o P15 strip14 3v3 o o 5V gnd o o gnd strip15 P16 o o P17 clock_3 kane16 P18 o o P19 strip17 strip18 P20 o o P21 strip19 strip20 P22 o o P23 strip21 3v3 o o 5v gnd o o gnd clock_4 P24 o o P25 strip22 kane23 P26 o o P27 strip24 strip25 P28 o o P29 strip26 strip27 P30 o o P31 clock_5 3v3 o o 5v gnd o o gnd strip28 P32 o o P33 strip29 strip30 P34 o o P35 strip31 strip32 P36 o o P37 strip33 clock_6 P38 o o P39 strip34 3v3 o o 5v gnd o o gnd strip35 P30 o o P41 strip36 strip37 P42 o o P43 strip38 strip39 P44 o o P45 clock_7 strip40 P46 o o P47 strip41 3c3 o o 5v gnd o o gnd strip42 P48 o o P49 strip43 strip44 P50 o o P51 strip45 clock_8 P52 o o P53 strip46 strip47 P54 o o P55 strip48 3v3 o o 5v gnd o o gnd strip49 P56 o o P57 strip50 strip51 P58 o o P59 clock_9 P60 o o P61 tx P62 o o P63 rx 3v3 o o 5v } '========================================================== var parms[5] '========================================================== pub start(clkf,strips,strip_length,basepin,addr) parms[0] := clkf parms[1] := strips parms[2] := strip_length parms[3] := basepin parms[4] := addr coginit(16,@ws2812,@parms) '========================================================= dat org ws2812 setq #5 'get parameters rdlong _clkf,ptra qdiv _clkf,##1_000_000 'calc delays getqx t_us qmul t_us,#50 getqx ws2812_load qmul t_us,#200 getqx t_200ns qdiv t_200ns,##1000 getqx t_200ns mov next_strip,_strip_length mul next_strip,#4 'Build color byte waveform patterns in LUTRAM for sync_tx smartpins 'e.g. byte $8c becomes %001_001_011_011_001_001_001_011 mov index,#0 build mov count,#8 'number of bits mov pa,index mov pb,#0 .loop testb pa,#7 wc shl pb,#3 or pb,#1 '0 = %100 (1/3 t) if_c or pb,#%10 '1 = %110 (2/3 t) shl pa,#1 djnz count,#.loop shl pb,#32-24 rev pb 'prepare for msb shifted first wrlut pb,index incmod index,#255 wz if_nz jmp #build 'configure smartpins and build pin list mov pinx,#0 mov pin,_basepin mov pb,_strips mov tclk,_basepin add tclk,#3 mov idx,#pin_list mov idx2,#clk_list mov clk_count,#0 call #init_tclk init cmp pinx,#3 wz if_e add pin,#1 'skip clock pin mov temp,tclk sub temp,pin and temp,#7 mov ax,#%1_11100_0 'sync tx mode setnib ax,temp,#6 'pinB select (clock source) wrpin ax,pin wxpin #%1_00000 | 24-1,pin 'start/stop mode 24 bits dirh pin 'enable smartpin altd idx,autoinc mov 0-0,pin 'save pin to list add pin,#1 incmod pinx,#5 wz if_z add tclk,#7 if_z call #init_tclk 'add new clock pin djnz pb,#init '=============================================================================== '=============================================================================== mainloop mov ptra,_led_buffer mov ptrb,ptra mov dx,_strip_length '3 bytes per led mul dx,#3 mov ex,#0 .new_strip mov ptra,ptrb 'get buffer address mov idx,#pin_list 'start of pin list rep @.sync_tx_loop,_strips 'load all sync_tx pins rdbyte ax,ptra wc 'get color byte rdlut ax,ax 'convert to 24 bit pattern alts idx,autoinc wypin ax,0-0 'load smartpin with pattern add ptra,next_strip .sync_tx_loop mov idx2,#clk_list 'start of clock list rep @.clock_loop,clk_count alts idx2,autoinc mov bx,0-0 wypin #24 * 2,bx 'start smartpin .clock_loop add ptrb,#1 incmod ex,#2 wz 'rgb byte select if_z add ptrb,#1 '4 testp bx wc 'wait for last transition end if_nc jmp #$-1 djnz dx,#.new_strip waitx ws2812_load 'data low for >50uS = reset jmp #mainloop init_tclk altd idx2,autoinc mov 0-0,tclk 'save clock pin wrpin #%1_00101_0,tclk 'transition mode wxpin t_200ns,tclk '200uS base period dirh tclk 'enable smartpin _ret_ add clk_count,#1 t_us long 0 ws2812_load long 0 t_200ns long 0 next_strip long 0 autoinc long 1 << 9 clk_count long 0 pin long 0 tclk long 0 temp long 0 idx long 0 idx2 long 0 pinx long 0 index long 0 count long 0 ax long 0 bx long 0 cx long 0 dx long 0 ex long 0 _clkf long 0 _strips long 0 _strip_length long 0 _basepin long 0 _led_buffer long 0 pin_list long 0[52] clk_list long 0[10]