TASMC51 V1.1 TAQOZ_Asm_Check PAGE 1 8051 Macro Assembler TASMC51 Version 1.1 ============================================ Source File: C:\Jim\TSim51\EFM8\TAQOZ_Asm_Check.asm Object File(s): C:\Jim\TSim51\EFM8\TAQOZ_Asm_Check.obj List File: C:\Jim\TSim51\EFM8\TAQOZ_Asm_Check.lst Line I Addr Code Source 1: ;------------------------------------------------------------------------------ 2: 3: $NOMOD51 4: $TITLE ( TAQOZ_Asm_Check ) 5: $INCLUDE(SI_EFM8BB1_Defs.inc) ; SFR defines, 6: 1 ;------------------------------------------------------------------------------ 7: 1 ; Copyright 2014 Silicon Laboratories, Inc. 8: 1 ; All rights reserved. This program and the accompanying materials 9: 1 ; are made available under the terms of the Silicon Laboratories End User 10: 1 ; License Agreement which accompanies this distribution, and is available at 11: 1 ; http://developer.silabs.com/legal/version/v11/Silicon_Labs_Software_License_Agreement.txt 12: 1 ; Original content and implementation provided by Silicon Laboratories. 13: 1 ;------------------------------------------------------------------------------ 14: 1 ;Supported Devices: 15: 1 ; EFM8BB10F2G 16: 1 ; EFM8BB10F4G 17: 1 ; EFM8BB10F8G 18: 1 ; EFM8BB10F8G 19: 1 ; EFM8BB10F8G 20: 1 21: 1 ;----------------------------------------------------------------------------- 22: 1 ; Register Definitions 23: 1 ;----------------------------------------------------------------------------- 24: 1 D E0 ACC DATA 0E0H; Accumulator 25: 1 D B3 ADC0AC DATA 0B3H; ADC0 Accumulator Configuration 26: 1 D BC ADC0CF DATA 0BCH; ADC0 Configuration 27: 1 D E8 ADC0CN0 DATA 0E8H; ADC0 Control 0 28: 1 D B2 ADC0CN1 DATA 0B2H; ADC0 Control 1 29: 1 D C4 ADC0GTH DATA 0C4H; ADC0 Greater-Than High Byte 30: 1 D C3 ADC0GTL DATA 0C3H; ADC0 Greater-Than Low Byte 31: 1 D BE ADC0H DATA 0BEH; ADC0 Data Word High Byte 32: 1 D BD ADC0L DATA 0BDH; ADC0 Data Word Low Byte 33: 1 D C6 ADC0LTH DATA 0C6H; ADC0 Less-Than High Byte 34: 1 D C5 ADC0LTL DATA 0C5H; ADC0 Less-Than Low Byte 35: 1 D BB ADC0MX DATA 0BBH; ADC0 Multiplexer Selection 36: 1 D DF ADC0PWR DATA 0DFH; ADC0 Power Control 37: 1 D B9 ADC0TK DATA 0B9H; ADC0 Burst Mode Track Time 38: 1 D F0 B DATA 0F0H; B Register 39: 1 D 8E CKCON0 DATA 08EH; Clock Control 0 40: 1 D A9 CLKSEL DATA 0A9H; Clock Select 41: 1 D 9B CMP0CN0 DATA 09BH; Comparator 0 Control 0 42: 1 D 9D CMP0MD DATA 09DH; Comparator 0 Mode 43: 1 D 9F CMP0MX DATA 09FH; Comparator 0 Multiplexer Selection 44: 1 D BF CMP1CN0 DATA 0BFH; Comparator 1 Control 0 45: 1 D AB CMP1MD DATA 0ABH; Comparator 1 Mode 46: 1 D AA CMP1MX DATA 0AAH; Comparator 1 Multiplexer Selection 47: 1 D D2 CRC0AUTO DATA 0D2H; CRC0 Automatic Control 48: 1 D CE CRC0CN0 DATA 0CEH; CRC0 Control 0 49: 1 D D3 CRC0CNT DATA 0D3H; CRC0 Automatic Flash Sector Count 50: 1 D DE CRC0DAT DATA 0DEH; CRC0 Data Output 51: 1 D CF CRC0FLIP DATA 0CFH; CRC0 Bit Flip 52: 1 D DD CRC0IN DATA 0DDH; CRC0 Data Input 53: 1 D AD DERIVID DATA 0ADH; Derivative Identification 54: 1 D B5 DEVICEID DATA 0B5H; Device Identification 55: 1 D 83 DPH DATA 083H; Data Pointer High 56: 1 D 82 DPL DATA 082H; Data Pointer Low 57: 1 D E6 EIE1 DATA 0E6H; Extended Interrupt Enable 1 58: 1 D F3 EIP1 DATA 0F3H; Extended Interrupt Priority 1 59: 1 D B7 FLKEY DATA 0B7H; Flash Lock and Key 60: 1 D C7 HFO0CAL DATA 0C7H; High Frequency Oscillator 0 Calibration 61: 1 D A8 IE DATA 0A8H; Interrupt Enable 62: 1 D B8 IP DATA 0B8H; Interrupt Priority 63: 1 D E4 IT01CF DATA 0E4H; INT0/INT1 Configuration 64: 1 D B1 LFO0CN DATA 0B1H; Low Frequency Oscillator Control 65: 1 D 80 P0 DATA 080H; Port 0 Pin Latch 66: 1 D FE P0MASK DATA 0FEH; Port 0 Mask 67: 1 D FD P0MAT DATA 0FDH; Port 0 Match 68: 1 D F1 P0MDIN DATA 0F1H; Port 0 Input Mode 69: 1 D A4 P0MDOUT DATA 0A4H; Port 0 Output Mode 70: 1 D D4 P0SKIP DATA 0D4H; Port 0 Skip 71: 1 D 90 P1 DATA 090H; Port 1 Pin Latch 72: 1 D EE P1MASK DATA 0EEH; Port 1 Mask 73: 1 D ED P1MAT DATA 0EDH; Port 1 Match 74: 1 D F2 P1MDIN DATA 0F2H; Port 1 Input Mode 75: 1 D A5 P1MDOUT DATA 0A5H; Port 1 Output Mode 76: 1 D D5 P1SKIP DATA 0D5H; Port 1 Skip 77: 1 D A0 P2 DATA 0A0H; Port 2 Pin Latch 78: 1 D A6 P2MDOUT DATA 0A6H; Port 2 Output Mode 79: 1 D 9E PCA0CENT DATA 09EH; PCA Center Alignment Enable 80: 1 D 9C PCA0CLR DATA 09CH; PCA Comparator Clear Control 81: 1 D D8 PCA0CN0 DATA 0D8H; PCA Control 82: 1 D FC PCA0CPH0 DATA 0FCH; PCA Channel 0 Capture Module High Byte 83: 1 D EA PCA0CPH1 DATA 0EAH; PCA Channel 1 Capture Module High Byte 84: 1 D EC PCA0CPH2 DATA 0ECH; PCA Channel 2 Capture Module High Byte 85: 1 D FB PCA0CPL0 DATA 0FBH; PCA Channel 0 Capture Module Low Byte 86: 1 D E9 PCA0CPL1 DATA 0E9H; PCA Channel 1 Capture Module Low Byte 87: 1 D EB PCA0CPL2 DATA 0EBH; PCA Channel 2 Capture Module Low Byte 88: 1 D DA PCA0CPM0 DATA 0DAH; PCA Channel 0 Capture/Compare Mode 89: 1 D DB PCA0CPM1 DATA 0DBH; PCA Channel 1 Capture/Compare Mode 90: 1 D DC PCA0CPM2 DATA 0DCH; PCA Channel 2 Capture/Compare Mode 91: 1 D FA PCA0H DATA 0FAH; PCA Counter/Timer High Byte 92: 1 D F9 PCA0L DATA 0F9H; PCA Counter/Timer Low Byte 93: 1 D D9 PCA0MD DATA 0D9H; PCA Mode 94: 1 D 96 PCA0POL DATA 096H; PCA Output Polarity 95: 1 D F7 PCA0PWM DATA 0F7H; PCA PWM Configuration 96: 1 D 87 PCON0 DATA 087H; Power Control 97: 1 D F6 PRTDRV DATA 0F6H; Port Drive Strength 98: 1 D 8F PSCTL DATA 08FH; Program Store Control 99: 1 D D0 PSW DATA 0D0H; Program Status Word 100: 1 D D1 REF0CN DATA 0D1H; Voltage Reference Control 101: 1 D C9 REG0CN DATA 0C9H; Voltage Regulator 0 Control 102: 1 D B6 REVID DATA 0B6H; Revision Identifcation 103: 1 D EF RSTSRC DATA 0EFH; Reset Source 104: 1 D 99 SBUF0 DATA 099H; UART0 Serial Port Data Buffer 105: 1 D 98 SCON0 DATA 098H; UART0 Serial Port Control 106: 1 D D6 SMB0ADM DATA 0D6H; SMBus 0 Slave Address Mask 107: 1 D D7 SMB0ADR DATA 0D7H; SMBus 0 Slave Address 108: 1 D C1 SMB0CF DATA 0C1H; SMBus 0 Configuration 109: 1 D C0 SMB0CN0 DATA 0C0H; SMBus 0 Control 110: 1 D C2 SMB0DAT DATA 0C2H; SMBus 0 Data 111: 1 D AC SMB0TC DATA 0ACH; SMBus 0 Timing and Pin Control 112: 1 D 81 SP DATA 081H; Stack Pointer 113: 1 D A1 SPI0CFG DATA 0A1H; SPI0 Configuration 114: 1 D A2 SPI0CKR DATA 0A2H; SPI0 Clock Rate 115: 1 D F8 SPI0CN0 DATA 0F8H; SPI0 Control 116: 1 D A3 SPI0DAT DATA 0A3H; SPI0 Data 117: 1 D 88 TCON DATA 088H; Timer 0/1 Control 118: 1 D 8C TH0 DATA 08CH; Timer 0 High Byte 119: 1 D 8D TH1 DATA 08DH; Timer 1 High Byte 120: 1 D 8A TL0 DATA 08AH; Timer 0 Low Byte 121: 1 D 8B TL1 DATA 08BH; Timer 1 Low Byte 122: 1 D 89 TMOD DATA 089H; Timer 0/1 Mode 123: 1 D C8 TMR2CN0 DATA 0C8H; Timer 2 Control 0 124: 1 D CD TMR2H DATA 0CDH; Timer 2 High Byte 125: 1 D CC TMR2L DATA 0CCH; Timer 2 Low Byte 126: 1 D CB TMR2RLH DATA 0CBH; Timer 2 Reload High Byte 127: 1 D CA TMR2RLL DATA 0CAH; Timer 2 Reload Low Byte 128: 1 D 91 TMR3CN0 DATA 091H; Timer 3 Control 0 129: 1 D 95 TMR3H DATA 095H; Timer 3 High Byte 130: 1 D 94 TMR3L DATA 094H; Timer 3 Low Byte 131: 1 D 93 TMR3RLH DATA 093H; Timer 3 Reload High Byte 132: 1 D 92 TMR3RLL DATA 092H; Timer 3 Reload Low Byte 133: 1 D FF VDM0CN DATA 0FFH; Supply Monitor Control 134: 1 D 97 WDTCN DATA 097H; Watchdog Timer Control 135: 1 D E1 XBR0 DATA 0E1H; Port I/O Crossbar 0 136: 1 D E2 XBR1 DATA 0E2H; Port I/O Crossbar 1 137: 1 D E3 XBR2 DATA 0E3H; Port I/O Crossbar 2 138: 1 139: 1 ;------------------------------------------------------------------------------ 140: 1 ; 16-bit Register Definitions (may not work on all compilers) 141: 1 ;------------------------------------------------------------------------------ 142: 1 D C3 ADC0GT DATA 0C3H ; ADC0 Greater-Than Low Byte 143: 1 D BD ADC0 DATA 0BDH ; ADC0 Data Word Low Byte 144: 1 D C5 ADC0LT DATA 0C5H ; ADC0 Less-Than Low Byte 145: 1 D 82 DP DATA 082H ; Data Pointer Low 146: 1 D FB PCA0CP0 DATA 0FBH ; PCA Channel 0 Capture Module Low Byte 147: 1 D E9 PCA0CP1 DATA 0E9H ; PCA Channel 1 Capture Module Low Byte 148: 1 D EB PCA0CP2 DATA 0EBH ; PCA Channel 2 Capture Module Low Byte 149: 1 D F9 PCA0 DATA 0F9H ; PCA Counter/Timer Low Byte 150: 1 D CC TMR2 DATA 0CCH ; Timer 2 Low Byte 151: 1 D CA TMR2RL DATA 0CAH ; Timer 2 Reload Low Byte 152: 1 D 94 TMR3 DATA 094H ; Timer 3 Low Byte 153: 1 D 92 TMR3RL DATA 092H ; Timer 3 Reload Low Byte 154: 1 155: 1 ;------------------------------------------------------------------------------ 156: 1 ; Indirect Register Definitions 157: 1 ;------------------------------------------------------------------------------ 158: 1 159: 1 ;------------------------------------------------------------------------------ 160: 1 ; Bit Definitions 161: 1 ;------------------------------------------------------------------------------ 162: 1 163: 1 ; ACC 0xE0 (Accumulator) 164: 1 B E0 ACC_ACC0 BIT ACC.0 ; Accumulator Bit 0 165: 1 B E1 ACC_ACC1 BIT ACC.1 ; Accumulator Bit 1 166: 1 B E2 ACC_ACC2 BIT ACC.2 ; Accumulator Bit 2 167: 1 B E3 ACC_ACC3 BIT ACC.3 ; Accumulator Bit 3 168: 1 B E4 ACC_ACC4 BIT ACC.4 ; Accumulator Bit 4 169: 1 B E5 ACC_ACC5 BIT ACC.5 ; Accumulator Bit 5 170: 1 B E6 ACC_ACC6 BIT ACC.6 ; Accumulator Bit 6 171: 1 B E7 ACC_ACC7 BIT ACC.7 ; Accumulator Bit 7 172: 1 173: 1 ; ADC0CN0 0xE8 (ADC0 Control 0) 174: 1 B E8 ADC0CN0_ADCM0 BIT ADC0CN0.0 ; Start of Conversion Mode Select Bit 0 175: 1 B E9 ADC0CN0_ADCM1 BIT ADC0CN0.1 ; Start of Conversion Mode Select Bit 1 176: 1 B EA ADC0CN0_ADCM2 BIT ADC0CN0.2 ; Start of Conversion Mode Select Bit 2 177: 1 B EB ADC0CN0_ADWINT BIT ADC0CN0.3 ; Window Compare Interrupt Flag 178: 1 B EC ADC0CN0_ADBUSY BIT ADC0CN0.4 ; ADC Busy 179: 1 B ED ADC0CN0_ADINT BIT ADC0CN0.5 ; Conversion Complete Interrupt Flag 180: 1 B EE ADC0CN0_ADBMEN BIT ADC0CN0.6 ; Burst Mode Enable 181: 1 B EF ADC0CN0_ADEN BIT ADC0CN0.7 ; ADC Enable 182: 1 183: 1 ; B 0xF0 (B Register) 184: 1 B F0 B_B0 BIT B.0 ; B Register Bit 0 185: 1 B F1 B_B1 BIT B.1 ; B Register Bit 1 186: 1 B F2 B_B2 BIT B.2 ; B Register Bit 2 187: 1 B F3 B_B3 BIT B.3 ; B Register Bit 3 188: 1 B F4 B_B4 BIT B.4 ; B Register Bit 4 189: 1 B F5 B_B5 BIT B.5 ; B Register Bit 5 190: 1 B F6 B_B6 BIT B.6 ; B Register Bit 6 191: 1 B F7 B_B7 BIT B.7 ; B Register Bit 7 192: 1 193: 1 ; IE 0xA8 (Interrupt Enable) 194: 1 B A8 IE_EX0 BIT IE.0 ; External Interrupt 0 Enable 195: 1 B A9 IE_ET0 BIT IE.1 ; Timer 0 Interrupt Enable 196: 1 B AA IE_EX1 BIT IE.2 ; External Interrupt 1 Enable 197: 1 B AB IE_ET1 BIT IE.3 ; Timer 1 Interrupt Enable 198: 1 B AC IE_ES0 BIT IE.4 ; UART0 Interrupt Enable 199: 1 B AD IE_ET2 BIT IE.5 ; Timer 2 Interrupt Enable 200: 1 B AE IE_ESPI0 BIT IE.6 ; SPI0 Interrupt Enable 201: 1 B AF IE_EA BIT IE.7 ; All Interrupts Enable 202: 1 203: 1 ; IP 0xB8 (Interrupt Priority) 204: 1 B B8 IP_PX0 BIT IP.0 ; External Interrupt 0 Priority Control 205: 1 B B9 IP_PT0 BIT IP.1 ; Timer 0 Interrupt Priority Control 206: 1 B BA IP_PX1 BIT IP.2 ; External Interrupt 1 Priority Control 207: 1 B BB IP_PT1 BIT IP.3 ; Timer 1 Interrupt Priority Control 208: 1 B BC IP_PS0 BIT IP.4 ; UART0 Interrupt Priority Control 209: 1 B BD IP_PT2 BIT IP.5 ; Timer 2 Interrupt Priority Control 210: 1 B BE IP_PSPI0 BIT IP.6 ; Serial Peripheral Interface (SPI0) Interrupt Priority Control 211: 1 212: 1 ; P0 0x80 (Port 0 Pin Latch) 213: 1 B 80 P0_B0 BIT P0.0 ; Port 0 Bit 0 Latch 214: 1 B 81 P0_B1 BIT P0.1 ; Port 0 Bit 1 Latch 215: 1 B 82 P0_B2 BIT P0.2 ; Port 0 Bit 2 Latch 216: 1 B 83 P0_B3 BIT P0.3 ; Port 0 Bit 3 Latch 217: 1 B 84 P0_B4 BIT P0.4 ; Port 0 Bit 4 Latch 218: 1 B 85 P0_B5 BIT P0.5 ; Port 0 Bit 5 Latch 219: 1 B 86 P0_B6 BIT P0.6 ; Port 0 Bit 6 Latch 220: 1 B 87 P0_B7 BIT P0.7 ; Port 0 Bit 7 Latch 221: 1 222: 1 ; P1 0x90 (Port 1 Pin Latch) 223: 1 B 90 P1_B0 BIT P1.0 ; Port 1 Bit 0 Latch 224: 1 B 91 P1_B1 BIT P1.1 ; Port 1 Bit 1 Latch 225: 1 B 92 P1_B2 BIT P1.2 ; Port 1 Bit 2 Latch 226: 1 B 93 P1_B3 BIT P1.3 ; Port 1 Bit 3 Latch 227: 1 B 94 P1_B4 BIT P1.4 ; Port 1 Bit 4 Latch 228: 1 B 95 P1_B5 BIT P1.5 ; Port 1 Bit 5 Latch 229: 1 B 96 P1_B6 BIT P1.6 ; Port 1 Bit 6 Latch 230: 1 B 97 P1_B7 BIT P1.7 ; Port 1 Bit 7 Latch 231: 1 232: 1 ; P2 0xA0 (Port 2 Pin Latch) 233: 1 B A0 P2_B0 BIT P2.0 ; Port 2 Bit 0 Latch 234: 1 B A1 P2_B1 BIT P2.1 ; Port 2 Bit 1 Latch 235: 1 236: 1 ; PCA0CN0 0xD8 (PCA Control) 237: 1 B D8 PCA0CN0_CCF0 BIT PCA0CN0.0 ; PCA Module 0 Capture/Compare Flag 238: 1 B D9 PCA0CN0_CCF1 BIT PCA0CN0.1 ; PCA Module 1 Capture/Compare Flag 239: 1 B DA PCA0CN0_CCF2 BIT PCA0CN0.2 ; PCA Module 2 Capture/Compare Flag 240: 1 B DE PCA0CN0_CR BIT PCA0CN0.6 ; PCA Counter/Timer Run Control 241: 1 B DF PCA0CN0_CF BIT PCA0CN0.7 ; PCA Counter/Timer Overflow Flag 242: 1 243: 1 ; PSW 0xD0 (Program Status Word) 244: 1 B D0 PSW_PARITY BIT PSW.0 ; Parity Flag 245: 1 B D1 PSW_F1 BIT PSW.1 ; User Flag 1 246: 1 B D2 PSW_OV BIT PSW.2 ; Overflow Flag 247: 1 B D3 PSW_RS0 BIT PSW.3 ; Register Bank Select Bit 0 248: 1 B D4 PSW_RS1 BIT PSW.4 ; Register Bank Select Bit 1 249: 1 B D5 PSW_F0 BIT PSW.5 ; User Flag 0 250: 1 B D6 PSW_AC BIT PSW.6 ; Auxiliary Carry Flag 251: 1 B D7 PSW_CY BIT PSW.7 ; Carry Flag 252: 1 253: 1 ; SCON0 0x98 (UART0 Serial Port Control) 254: 1 B 98 SCON0_RI BIT SCON0.0 ; Receive Interrupt Flag 255: 1 B 99 SCON0_TI BIT SCON0.1 ; Transmit Interrupt Flag 256: 1 B 9A SCON0_RB8 BIT SCON0.2 ; Ninth Receive Bit 257: 1 B 9B SCON0_TB8 BIT SCON0.3 ; Ninth Transmission Bit 258: 1 B 9C SCON0_REN BIT SCON0.4 ; Receive Enable 259: 1 B 9D SCON0_MCE BIT SCON0.5 ; Multiprocessor Communication Enable 260: 1 B 9F SCON0_SMODE BIT SCON0.7 ; Serial Port 0 Operation Mode 261: 1 262: 1 ; SMB0CN0 0xC0 (SMBus 0 Control) 263: 1 B C0 SMB0CN0_SI BIT SMB0CN0.0 ; SMBus Interrupt Flag 264: 1 B C1 SMB0CN0_ACK BIT SMB0CN0.1 ; SMBus Acknowledge 265: 1 B C2 SMB0CN0_ARBLOST BIT SMB0CN0.2 ; SMBus Arbitration Lost Indicator 266: 1 B C3 SMB0CN0_ACKRQ BIT SMB0CN0.3 ; SMBus Acknowledge Request 267: 1 B C4 SMB0CN0_STO BIT SMB0CN0.4 ; SMBus Stop Flag 268: 1 B C5 SMB0CN0_STA BIT SMB0CN0.5 ; SMBus Start Flag 269: 1 B C6 SMB0CN0_TXMODE BIT SMB0CN0.6 ; SMBus Transmit Mode Indicator 270: 1 B C7 SMB0CN0_MASTER BIT SMB0CN0.7 ; SMBus Master/Slave Indicator 271: 1 272: 1 ; SPI0CN0 0xF8 (SPI0 Control) 273: 1 B F8 SPI0CN0_SPIEN BIT SPI0CN0.0 ; SPI0 Enable 274: 1 B F9 SPI0CN0_TXBMT BIT SPI0CN0.1 ; Transmit Buffer Empty 275: 1 B FA SPI0CN0_NSSMD0 BIT SPI0CN0.2 ; Slave Select Mode Bit 0 276: 1 B FB SPI0CN0_NSSMD1 BIT SPI0CN0.3 ; Slave Select Mode Bit 1 277: 1 B FC SPI0CN0_RXOVRN BIT SPI0CN0.4 ; Receive Overrun Flag 278: 1 B FD SPI0CN0_MODF BIT SPI0CN0.5 ; Mode Fault Flag 279: 1 B FE SPI0CN0_WCOL BIT SPI0CN0.6 ; Write Collision Flag 280: 1 B FF SPI0CN0_SPIF BIT SPI0CN0.7 ; SPI0 Interrupt Flag 281: 1 282: 1 ; TCON 0x88 (Timer 0/1 Control) 283: 1 B 88 TCON_IT0 BIT TCON.0 ; Interrupt 0 Type Select 284: 1 B 89 TCON_IE0 BIT TCON.1 ; External Interrupt 0 285: 1 B 8A TCON_IT1 BIT TCON.2 ; Interrupt 1 Type Select 286: 1 B 8B TCON_IE1 BIT TCON.3 ; External Interrupt 1 287: 1 B 8C TCON_TR0 BIT TCON.4 ; Timer 0 Run Control 288: 1 B 8D TCON_TF0 BIT TCON.5 ; Timer 0 Overflow Flag 289: 1 B 8E TCON_TR1 BIT TCON.6 ; Timer 1 Run Control 290: 1 B 8F TCON_TF1 BIT TCON.7 ; Timer 1 Overflow Flag 291: 1 292: 1 ; TMR2CN0 0xC8 (Timer 2 Control 0) 293: 1 B C8 TMR2CN0_T2XCLK BIT TMR2CN0.0 ; Timer 2 External Clock Select 294: 1 B CA TMR2CN0_TR2 BIT TMR2CN0.2 ; Timer 2 Run Control 295: 1 B CB TMR2CN0_T2SPLIT BIT TMR2CN0.3 ; Timer 2 Split Mode Enable 296: 1 B CC TMR2CN0_TF2CEN BIT TMR2CN0.4 ; Timer 2 Capture Enable 297: 1 B CD TMR2CN0_TF2LEN BIT TMR2CN0.5 ; Timer 2 Low Byte Interrupt Enable 298: 1 B CE TMR2CN0_TF2L BIT TMR2CN0.6 ; Timer 2 Low Byte Overflow Flag 299: 1 B CF TMR2CN0_TF2H BIT TMR2CN0.7 ; Timer 2 High Byte Overflow Flag 300: 1 301: 1 ;------------------------------------------------------------------------------ 302: 1 ; Interrupt Definitions 303: 1 ;------------------------------------------------------------------------------ 304: 1 = 00 INT0_IRQn EQU 0 ; External Interrupt 0 305: 1 = 01 TIMER0_IRQn EQU 1 ; Timer 0 Overflow 306: 1 = 02 INT1_IRQn EQU 2 ; External Interrupt 1 307: 1 = 03 TIMER1_IRQn EQU 3 ; Timer 1 Overflow 308: 1 = 04 UART0_IRQn EQU 4 ; UART0 309: 1 = 05 TIMER2_IRQn EQU 5 ; Timer 2 Overflow / Capture 310: 1 = 06 SPI0_IRQn EQU 6 ; SPI0 311: 1 = 07 SMBUS0_IRQn EQU 7 ; SMBus0 312: 1 = 08 PMATCH_IRQn EQU 8 ; Port Match 313: 1 = 09 ADC0WC_IRQn EQU 9 ; ADC0 Window Compare 314: 1 = 0A ADC0EOC_IRQn EQU 10 ; ADC0 End of Conversion 315: 1 = 0B PCA0_IRQn EQU 11 ; PCA0 316: 1 = 0C CMP0_IRQn EQU 12 ; Comparator 0 317: 1 = 0D CMP1_IRQn EQU 13 ; Comparator 1 318: 1 = 0E TIMER3_IRQn EQU 14 ; Timer 3 Overflow / Capture 319: cseg at 0000h ;<< Reset vector 320: 321: ; TAQOZ_Asm pasted here and edited $nn to 0xnn for hex support. 322: 323: 324: = AD PID equ 0xAD 325: = B6 RID equ 0xB6 326: = 0C RXD0 equ 12 327: = A5 K1 equ 0xA5 328: = 40 VARS equ 0x40 329: 330: org 0x180 331: 0180 D4 MAIN: DA A ; fixed mnemonic, was just DA 332: 0181 90 04 D2 MOV DPTR,#1234 333: 0184 54 34 ANL A,#0x34 334: 0186 82 34 ANL C,0x34 335: 0188 5F ANL A,R7 336: 0189 24 34 ADD A,#0x34 337: 018B 25 40 ADD A,VARS 338: ; MOV A,#0x100 ; gives range check error, loads 0x00, 2 byte opcode 339: 018D 75 E0 00 MOV ACC,#0x100 ; gives range check error, loads 0x00, 3 byte opcode ^ (TAQOZ_Asm_Check.asm 26,33) ERROR: Overflow error 340: 0190 02 01 80 LJMP MAIN 341: 0193 40 EB JC MAIN 342: 0195 20 0C E8 JB RXD0,MAIN 343: 0198 30 A5 E5 JNB 0xA5,MAIN 344: 019B 30 A5 E2 JNB K1,MAIN 345: 019E E4 CLR A 346: 019F C3 CLR C 347: 01A0 C2 0C CLR RXD0 348: 01A2 D3 SETB C 349: 01A3 20 45 DA JB 0x45,MAIN 350: 01A6 12 01 B9 LCALL FWD 351: 01A9 73 JMP @A+DPTR 352: 01AA 50 D4 JNC MAIN 353: 01AC 70 D2 JNZ MAIN 354: 01AE 60 D0 JZ MAIN 355: 01B0 40 CE JC MAIN 356: 01B2 80 CC SJMP MAIN 357: 01B4 02 01 80 LJMP MAIN 358: 01B7 D2 0C SETB RXD0 359: 01B9 C3 FWD: CLR C 360: 01BA EF MOV A,R7 361: 01BB F8 MOV R0,A 362: 01BC F6 MOV @R0,A 363: 01BD F7 MOV @R1,A 364: 01BE E6 MOV A,@R0 365: 01BF E7 MOV A,@R1 366: 01C0 E8 MOV A,R0 367: 01C1 EF MOV A,R7 368: 01C2 46 ORL A,@R0 369: 01C3 47 ORL A,@R1 370: 01C4 48 ORL A,R0 371: 01C5 4F ORL A,R7 372: 01C6 96 SUBB A,@R0 373: 01C7 97 SUBB A,@R1 374: 01C8 98 SUBB A,R0 375: 01C9 9F SUBB A,R7 376: 01CA 06 INC @R0 377: 01CB 07 INC @R1 378: 01CC 08 INC R0 379: 01CD 0F INC R7 380: 01CE A3 INC DPTR 381: 01CF 04 INC A 382: 01D0 05 40 INC VARS 383: 01D2 26 ADD A,@R0 384: 01D3 28 ADD A,R0 385: 01D4 2F ADD A,R7 386: 01D5 22 RET 387: 388: = 84 mycon equ 0x84 389: 390: 01D6 22 PROC5: ret 391: 392: 01D7 B4 FE FC PROC4: cjne A,#0FEh,PROC5 393: 01DA 85 C2 82 mov DPL, SMB0DAT ; was smbdat 394: 01DD 85 00 83 mov DPH,smbdir ^ (TAQOZ_Asm_Check.asm 81,22) ERROR: Label not found 395: 01E0 78 00 RDFL: mov r0,#auxbuf ; ^ (TAQOZ_Asm_Check.asm 82,22) ERROR: Label not found 396: 01E2 79 00 mov r1,#SMBTXSZ2 ^ (TAQOZ_Asm_Check.asm 83,22) ERROR: Label not found 397: 01E4 E4 rdflp: clr A 398: 01E5 93 movc A,@A+DPTR 399: 01E6 F6 mov @r0,A 400: 01E7 05 82 inc DPL 401: 01E9 08 inc r0 402: 01EA D9 F8 djnz r1,rdflp 403: 01EC 75 00 00 mov smbTxRd,#SMBTXSZ ^ (TAQOZ_Asm_Check.asm 90,18) ERROR: Label not found 404: 01EF 22 ret 405: 01F0 B4 FD E4 PROC3: cjne A,#0FDh,PROC4 406: 01F3 75 82 00 mov DPL,#TITLE ; ^ (TAQOZ_Asm_Check.asm 93,23) ERROR: Label not found 407: 01F6 75 83 00 mov DPH,#TITLE ; ^ (TAQOZ_Asm_Check.asm 94,23) ERROR: Label not found 408: 01F9 80 E5 jmp RDFL 409: 01FB B4 03 F2 PROC2A: cjne A,#3,PROC3 410: 01FE 75 A5 00 mov P1MDOUT,#0 411: 0201 75 90 FF mov P1,#0FFh 412: 0204 22 ret 413: 0205 B4 02 F3 PROC2: cjne A,#2,PROC2A 414: 0208 85 00 A5 mov P1MDOUT,smbdat ^ (TAQOZ_Asm_Check.asm 101,26) ERROR: Label not found 415: 020B 22 ret 416: 020C B4 01 F6 PROC1: cjne A,#1,PROC2 417: 020F 85 00 90 mov P1,smbdat ^ (TAQOZ_Asm_Check.asm 104,21) ERROR: Label not found 418: 0212 85 00 A5 mov P1MDOUT,smbdir ^ (TAQOZ_Asm_Check.asm 105,26) ERROR: Label not found 419: 0215 22 ret 420: 421: 0216 PROCESS_SMB: 422: 0216 E5 00 mov A,smbcmd ^ (TAQOZ_Asm_Check.asm 109,20) ERROR: Label not found 423: 0218 44 00 orl A,#0 424: 021A 70 F0 jnz PROC1 425: 021C 22 ret 426: 427: 021D 80 F7 SJMP PROCESS_SMB 428: 021F 80 F5 JMP PROCESS_SMB 429: 0221 01 40 JMP 0x40 430: ^ (TAQOZ_Asm_Check.asm 117,1) ERROR: Missing END statement TASMC51 V1.1 TAQOZ_Asm_Check PAGE 2 L I S T O F F I L E S ========================= INDEX FILENAME -------------------------------------------------------------------------------------------------------------------------------------------------------------- 0 C:\Jim\TSim51\EFM8\TAQOZ_Asm_Check.asm 1 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TASMC51 V1.1 TAQOZ_Asm_Check PAGE 3 L I S T O F S Y M B O L S ============================= SYMBOL TYPE VALUE LINE FILE -------------------------------------------------------------------------------------------------------------------------------------------------------------- ??CODE_SIZE NUMBER 10000 ??DEVICE NUMBER 001E ??ERAM_SIZE NUMBER 10000 ??FDATA_SIZE NUMBER 10000 ??RAM_SIZE NUMBER 0100 ??TASMC51 NUMBER 8051 ??VERSION NUMBER 0101 ??_AT89C2051_ NUMBER 00 ??_AT89C4051_ NUMBER 01 ??_AT89C51ED2_ NUMBER 02 ??_AT89C51IC2_ NUMBER 03 ??_AT89C51ID2_ NUMBER 04 ??_AT89C51RB2_ NUMBER 05 ??_AT89C51RC2_ NUMBER 06 ??_AT89C51RD2_ NUMBER 07 ??_AT89C51RE2_ NUMBER 08 ??_AT89C55WD_ NUMBER 09 ??_AT89LP2052_ NUMBER 0A ??_AT89LP213_ NUMBER 0C ??_AT89LP214_ NUMBER 0D ??_AT89LP216_ NUMBER 0E ??_AT89LP4052_ NUMBER 0B ??_AT89LP51ED2_ NUMBER 11 ??_AT89LP51IC2_ NUMBER 12 ??_AT89LP51ID2_ NUMBER 13 ??_AT89LP51RB2_ NUMBER 14 ??_AT89LP51RC2_ NUMBER 15 ??_AT89LP51RD2_ NUMBER 16 ??_AT89LP51_ NUMBER 0F ??_AT89LP52_ NUMBER 10 ??_AT89S2051_ NUMBER 17 ??_AT89S4051_ NUMBER 18 ??_AT89S51_ NUMBER 19 ??_AT89S52_ NUMBER 1A ??_AT89S8253_ NUMBER 1B ??_C8051F850_ NUMBER 1D ??_EFM8UB10F16G-QFN20_ NUMBER 20 ??_EFM8UB10F16G-QFN28_ NUMBER 1E ??_EFM8UB10F8G-QFN20_ NUMBER 21 ??_EFM8UB11F16G-QSOP24_ NUMBER 1F ??__ NUMBER 1C ??__ NUMBER 22 ACC DATA E0 19 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ACC_ACC0 BIT E0 159 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ACC_ACC1 BIT E1 160 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ACC_ACC2 BIT E2 161 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ACC_ACC3 BIT E3 162 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ACC_ACC4 BIT E4 163 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ACC_ACC5 BIT E5 164 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ACC_ACC6 BIT E6 165 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ACC_ACC7 BIT E7 166 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0 DATA BD 138 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0AC DATA B3 20 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0CF DATA BC 21 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0CN0 DATA E8 22 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0CN0_ADBMEN BIT EE 175 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0CN0_ADBUSY BIT EC 173 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0CN0_ADCM0 BIT E8 169 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0CN0_ADCM1 BIT E9 170 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0CN0_ADCM2 BIT EA 171 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0CN0_ADEN BIT EF 176 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0CN0_ADINT BIT ED 174 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0CN0_ADWINT BIT EB 172 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0CN1 DATA B2 23 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0EOC_IRQN NUMBER A 309 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0GT DATA C3 137 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0GTH DATA C4 24 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0GTL DATA C3 25 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0H DATA BE 26 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0L DATA BD 27 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0LT DATA C5 139 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0LTH DATA C6 28 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0LTL DATA C5 29 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0MX DATA BB 30 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0PWR DATA DF 31 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0TK DATA B9 32 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc ADC0WC_IRQN NUMBER 9 308 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc B DATA F0 33 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc B_B0 BIT F0 179 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc B_B1 BIT F1 180 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc B_B2 BIT F2 181 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc B_B3 BIT F3 182 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc B_B4 BIT F4 183 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc B_B5 BIT F5 184 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc B_B6 BIT F6 185 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc B_B7 BIT F7 186 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc CKCON0 DATA 8E 34 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc CLKSEL DATA A9 35 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc CMP0CN0 DATA 9B 36 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc CMP0MD DATA 9D 37 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc CMP0MX DATA 9F 38 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc CMP0_IRQN NUMBER C 311 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc CMP1CN0 DATA BF 39 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc CMP1MD DATA AB 40 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc CMP1MX DATA AA 41 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc CMP1_IRQN NUMBER D 312 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc CRC0AUTO DATA D2 42 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc CRC0CN0 DATA CE 43 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc CRC0CNT DATA D3 44 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc CRC0DAT DATA DE 45 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc CRC0FLIP DATA CF 46 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc CRC0IN DATA DD 47 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc DERIVID DATA AD 48 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc DEVICEID DATA B5 49 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc DP DATA 82 140 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc DPH DATA 83 50 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc DPL DATA 82 51 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc EIE1 DATA E6 52 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc EIP1 DATA F3 53 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc FLKEY DATA B7 54 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc FWD CODE 01B9 46 C:\Jim\TSim51\EFM8\TAQOZ_Asm_Check.asm HFO0CAL DATA C7 55 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc IE DATA A8 56 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc IE_EA BIT AF 196 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc IE_ES0 BIT AC 193 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc IE_ESPI0 BIT AE 195 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc IE_ET0 BIT A9 190 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc IE_ET1 BIT AB 192 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc IE_ET2 BIT AD 194 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc IE_EX0 BIT A8 189 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc IE_EX1 BIT AA 191 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc INT0_IRQN NUMBER 0 299 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc INT1_IRQN NUMBER 2 301 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc IP DATA B8 57 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc IP_PS0 BIT BC 203 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc IP_PSPI0 BIT BE 205 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc IP_PT0 BIT B9 200 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc IP_PT1 BIT BB 202 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc IP_PT2 BIT BD 204 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc IP_PX0 BIT B8 199 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc IP_PX1 BIT BA 201 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc IT01CF DATA E4 58 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc K1 NUMBER A5 14 C:\Jim\TSim51\EFM8\TAQOZ_Asm_Check.asm LFO0CN DATA B1 59 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc MAIN CODE 0180 18 C:\Jim\TSim51\EFM8\TAQOZ_Asm_Check.asm MYCON NUMBER 84 75 C:\Jim\TSim51\EFM8\TAQOZ_Asm_Check.asm P0 DATA 80 60 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P0MASK DATA FE 61 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P0MAT DATA FD 62 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P0MDIN DATA F1 63 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P0MDOUT DATA A4 64 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P0SKIP DATA D4 65 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P0_B0 BIT 80 208 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P0_B1 BIT 81 209 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P0_B2 BIT 82 210 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P0_B3 BIT 83 211 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P0_B4 BIT 84 212 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P0_B5 BIT 85 213 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P0_B6 BIT 86 214 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P0_B7 BIT 87 215 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P1 DATA 90 66 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P1MASK DATA EE 67 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P1MAT DATA ED 68 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P1MDIN DATA F2 69 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P1MDOUT DATA A5 70 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P1SKIP DATA D5 71 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P1_B0 BIT 90 218 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P1_B1 BIT 91 219 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P1_B2 BIT 92 220 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P1_B3 BIT 93 221 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P1_B4 BIT 94 222 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P1_B5 BIT 95 223 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P1_B6 BIT 96 224 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P1_B7 BIT 97 225 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P2 DATA A0 72 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P2MDOUT DATA A6 73 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P2_B0 BIT A0 228 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc P2_B1 BIT A1 229 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0 DATA F9 144 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0CENT DATA 9E 74 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0CLR DATA 9C 75 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0CN0 DATA D8 76 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0CN0_CCF0 BIT D8 232 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0CN0_CCF1 BIT D9 233 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0CN0_CCF2 BIT DA 234 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0CN0_CF BIT DF 236 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0CN0_CR BIT DE 235 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0CP0 DATA FB 141 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0CP1 DATA E9 142 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0CP2 DATA EB 143 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0CPH0 DATA FC 77 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0CPH1 DATA EA 78 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0CPH2 DATA EC 79 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0CPL0 DATA FB 80 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0CPL1 DATA E9 81 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0CPL2 DATA EB 82 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0CPM0 DATA DA 83 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0CPM1 DATA DB 84 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0CPM2 DATA DC 85 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0H DATA FA 86 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0L DATA F9 87 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0MD DATA D9 88 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0POL DATA 96 89 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0PWM DATA F7 90 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCA0_IRQN NUMBER B 310 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PCON0 DATA 87 91 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PID NUMBER AD 11 C:\Jim\TSim51\EFM8\TAQOZ_Asm_Check.asm PMATCH_IRQN NUMBER 8 307 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PROC1 CODE 020C 103 C:\Jim\TSim51\EFM8\TAQOZ_Asm_Check.asm PROC2 CODE 0205 100 C:\Jim\TSim51\EFM8\TAQOZ_Asm_Check.asm PROC2A CODE 01FB 96 C:\Jim\TSim51\EFM8\TAQOZ_Asm_Check.asm PROC3 CODE 01F0 92 C:\Jim\TSim51\EFM8\TAQOZ_Asm_Check.asm PROC4 CODE 01D7 79 C:\Jim\TSim51\EFM8\TAQOZ_Asm_Check.asm PROC5 CODE 01D6 77 C:\Jim\TSim51\EFM8\TAQOZ_Asm_Check.asm PROCESS_SMB CODE 0216 108 C:\Jim\TSim51\EFM8\TAQOZ_Asm_Check.asm PRTDRV DATA F6 92 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PSCTL DATA 8F 93 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PSW DATA D0 94 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PSW_AC BIT D6 245 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PSW_CY BIT D7 246 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PSW_F0 BIT D5 244 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PSW_F1 BIT D1 240 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PSW_OV BIT D2 241 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PSW_PARITY BIT D0 239 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PSW_RS0 BIT D3 242 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc PSW_RS1 BIT D4 243 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc RDFL CODE 01E0 82 C:\Jim\TSim51\EFM8\TAQOZ_Asm_Check.asm RDFLP CODE 01E4 84 C:\Jim\TSim51\EFM8\TAQOZ_Asm_Check.asm REF0CN DATA D1 95 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc REG0CN DATA C9 96 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc REVID DATA B6 97 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc RID NUMBER B6 12 C:\Jim\TSim51\EFM8\TAQOZ_Asm_Check.asm RSTSRC DATA EF 98 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc RXD0 NUMBER C 13 C:\Jim\TSim51\EFM8\TAQOZ_Asm_Check.asm SBUF0 DATA 99 99 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SCON0 DATA 98 100 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SCON0_MCE BIT 9D 254 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SCON0_RB8 BIT 9A 251 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SCON0_REN BIT 9C 253 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SCON0_RI BIT 98 249 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SCON0_SMODE BIT 9F 255 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SCON0_TB8 BIT 9B 252 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SCON0_TI BIT 99 250 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SMB0ADM DATA D6 101 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SMB0ADR DATA D7 102 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SMB0CF DATA C1 103 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SMB0CN0 DATA C0 104 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SMB0CN0_ACK BIT C1 259 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SMB0CN0_ACKRQ BIT C3 261 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SMB0CN0_ARBLOST BIT C2 260 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SMB0CN0_MASTER BIT C7 265 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SMB0CN0_SI BIT C0 258 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SMB0CN0_STA BIT C5 263 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SMB0CN0_STO BIT C4 262 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SMB0CN0_TXMODE BIT C6 264 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SMB0DAT DATA C2 105 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SMB0TC DATA AC 106 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SMBUS0_IRQN NUMBER 7 306 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SP DATA 81 107 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SPI0CFG DATA A1 108 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SPI0CKR DATA A2 109 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SPI0CN0 DATA F8 110 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SPI0CN0_MODF BIT FD 273 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SPI0CN0_NSSMD0 BIT FA 270 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SPI0CN0_NSSMD1 BIT FB 271 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SPI0CN0_RXOVRN BIT FC 272 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SPI0CN0_SPIEN BIT F8 268 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SPI0CN0_SPIF BIT FF 275 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SPI0CN0_TXBMT BIT F9 269 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SPI0CN0_WCOL BIT FE 274 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SPI0DAT DATA A3 111 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc SPI0_IRQN NUMBER 6 305 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TCON DATA 88 112 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TCON_IE0 BIT 89 279 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TCON_IE1 BIT 8B 281 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TCON_IT0 BIT 88 278 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TCON_IT1 BIT 8A 280 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TCON_TF0 BIT 8D 283 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TCON_TF1 BIT 8F 285 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TCON_TR0 BIT 8C 282 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TCON_TR1 BIT 8E 284 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TH0 DATA 8C 113 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TH1 DATA 8D 114 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TIMER0_IRQN NUMBER 1 300 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TIMER1_IRQN NUMBER 3 302 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TIMER2_IRQN NUMBER 5 304 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TIMER3_IRQN NUMBER E 313 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TL0 DATA 8A 115 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TL1 DATA 8B 116 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMOD DATA 89 117 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMR2 DATA CC 145 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMR2CN0 DATA C8 118 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMR2CN0_T2SPLIT BIT CB 290 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMR2CN0_T2XCLK BIT C8 288 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMR2CN0_TF2CEN BIT CC 291 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMR2CN0_TF2H BIT CF 294 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMR2CN0_TF2L BIT CE 293 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMR2CN0_TF2LEN BIT CD 292 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMR2CN0_TR2 BIT CA 289 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMR2H DATA CD 119 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMR2L DATA CC 120 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMR2RL DATA CA 146 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMR2RLH DATA CB 121 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMR2RLL DATA CA 122 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMR3 DATA 94 147 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMR3CN0 DATA 91 123 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMR3H DATA 95 124 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMR3L DATA 94 125 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMR3RL DATA 92 148 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMR3RLH DATA 93 126 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TMR3RLL DATA 92 127 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc UART0_IRQN NUMBER 4 303 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc VARS NUMBER 40 15 C:\Jim\TSim51\EFM8\TAQOZ_Asm_Check.asm VDM0CN DATA FF 128 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc WDTCN DATA 97 129 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc XBR0 DATA E1 130 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc XBR1 DATA E2 131 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc XBR2 DATA E3 132 C:\Jim\TSim51\EFM8\SI_EFM8BB1_Defs.inc TASMC51 V1.1 TAQOZ_Asm_Check PAGE 4 S E G M E N T U S A G E ========================= Code : 547 bytes of 65536 Data : 0 bytes of 128 IData : 0 bytes of 128 EData : 0 bytes of 8192 FData : 0 bytes of 0 UData : 0 bytes of 512 XData : 0 bytes of 65536 Bit : 0 bits of 128 Register banks used: - Errors: 12