clk ------------____________------------____________------------____________------------____________------------____________------------____________- | | | | | | | |-------+ | rdRAM Ic |-------+ | rdRAM Id |-------+ | rdRAM Ie | | | | | | | | | | | |---+ +----> rdRAM Db |------------> latch Db |---+ +----> rdRAM Dc |------------> latch Dc |---+ +----> rdRAM Dd |------------> latch Dd | |---+ +----> rdRAM Sb |------------> latch Sb |---+ +----> rdRAM Sc |------------> latch Sc |---+ +----> rdRAM Sd |------------> latch Sd | |---+ +----> latch Ib |------------> latch Ib |---+ +----> latch Ic |------------> latch Ic |---+ +----> latch Id |------------> latch Id | | | | | | | | | | | | +------------------ALU-----------> wrRAM Ra | +------------------ALU-----------> wrRAM Rb | +------------------ALU-----------> wrRAM Rc | | | | | | | | | | stall/done = 'gox' | | stall/done = 'gox' | | stall/done = 'gox' | | 'get' | done = 'go' | 'get' | done = 'go' | 'get' | done = 'go' | -- addressable registers -- -- addr read write name -- ---------------------------------------- -- -- 000-1F7 RAM RAM -- -- 1F8 PTRA RAM+PTRA PTRA -- 1F9 PTRB RAM+PTRB PTRB -- 1FA INA RAM INA -- 1FB INB RAM INB -- 1FC RAM RAM+OUTA OUTA -- 1FD RAM RAM+OUTB OUTB -- 1FE RAM RAM+DIRA DIRA -- 1FF RAM RAM+DIRB DIRB CZDS (for D column: W=write, M=modify, R=read, L=read/immediate) ---------------------------------------------------------------------------------------------------------------------- CZMS 0000000 CZI CCCC DDDDDDDDD SSSSSSSSS ROR D,S/# rot CZMS 0000001 CZI CCCC DDDDDDDDD SSSSSSSSS ROL D,S/# rot CZMS 0000010 CZI CCCC DDDDDDDDD SSSSSSSSS SHR D,S/# rot CZMS 0000011 CZI CCCC DDDDDDDDD SSSSSSSSS SHL D,S/# rot CZMS 0000100 CZI CCCC DDDDDDDDD SSSSSSSSS RCR D,S/# rot CZMS 0000101 CZI CCCC DDDDDDDDD SSSSSSSSS RCL D,S/# rot CZMS 0000110 CZI CCCC DDDDDDDDD SSSSSSSSS SAR D,S/# rot CZMS 0000111 CZI CCCC DDDDDDDDD SSSSSSSSS SAL D,S/# rot CZMS 0001000 CZI CCCC DDDDDDDDD SSSSSSSSS ADD D,S/# add CZMS 0001001 CZI CCCC DDDDDDDDD SSSSSSSSS ADDX D,S/# add CZMS 0001010 CZI CCCC DDDDDDDDD SSSSSSSSS ADDS D,S/# add CZMS 0001011 CZI CCCC DDDDDDDDD SSSSSSSSS ADDSX D,S/# add CZMS 0001100 CZI CCCC DDDDDDDDD SSSSSSSSS SUB D,S/# add CZMS 0001101 CZI CCCC DDDDDDDDD SSSSSSSSS SUBX D,S/# add CZMS 0001110 CZI CCCC DDDDDDDDD SSSSSSSSS SUBS D,S/# add CZMS 0001111 CZI CCCC DDDDDDDDD SSSSSSSSS SUBSX D,S/# add CZRS 0010000 CZI CCCC DDDDDDDDD SSSSSSSSS CMP D,S/# add CZRS 0010001 CZI CCCC DDDDDDDDD SSSSSSSSS CMPX D,S/# add CZRS 0010010 CZI CCCC DDDDDDDDD SSSSSSSSS CMPS D,S/# add CZRS 0010011 CZI CCCC DDDDDDDDD SSSSSSSSS CMPSX D,S/# add CZRS 0010100 CZI CCCC DDDDDDDDD SSSSSSSSS CMPR D,S/# add (compare reverse - S to D) CZRS 0010101 CZI CCCC DDDDDDDDD SSSSSSSSS CMPM D,S/# add (compare, MSB of result into C) CZMS 0010110 CZI CCCC DDDDDDDDD SSSSSSSSS SUBR D,S/# add (subtract reverse - D from S) CZMS 0010111 CZI CCCC DDDDDDDDD SSSSSSSSS CMPSUB D,S/# add CZMS 0011000 CZI CCCC DDDDDDDDD SSSSSSSSS MIN D,S/# add CZMS 0011001 CZI CCCC DDDDDDDDD SSSSSSSSS MAX D,S/# add CZMS 0011010 CZI CCCC DDDDDDDDD SSSSSSSSS MINS D,S/# add CZMS 0011011 CZI CCCC DDDDDDDDD SSSSSSSSS MAXS D,S/# add CZMS 0011100 CZI CCCC DDDDDDDDD SSSSSSSSS SUMC D,S/# add CZMS 0011101 CZI CCCC DDDDDDDDD SSSSSSSSS SUMNC D,S/# add CZMS 0011110 CZI CCCC DDDDDDDDD SSSSSSSSS SUMZ D,S/# add CZMS 0011111 CZI CCCC DDDDDDDDD SSSSSSSSS SUMNZ D,S/# add CZMS 0100000 CZI CCCC DDDDDDDDD SSSSSSSSS ISOB D,S/# log CZMS 0100001 CZI CCCC DDDDDDDDD SSSSSSSSS NOTB D,S/# log CZMS 0100010 CZI CCCC DDDDDDDDD SSSSSSSSS CLRB D,S/# log CZMS 0100011 CZI CCCC DDDDDDDDD SSSSSSSSS SETB D,S/# log CZMS 0100100 CZI CCCC DDDDDDDDD SSSSSSSSS SETBC D,S/# log CZMS 0100101 CZI CCCC DDDDDDDDD SSSSSSSSS SETBNC D,S/# log CZMS 0100110 CZI CCCC DDDDDDDDD SSSSSSSSS SETBZ D,S/# log CZMS 0100111 CZI CCCC DDDDDDDDD SSSSSSSSS SETBNZ D,S/# log CZMS 0101000 CZI CCCC DDDDDDDDD SSSSSSSSS ANDN D,S/# log CZMS 0101001 CZI CCCC DDDDDDDDD SSSSSSSSS AND D,S/# log CZMS 0101010 CZI CCCC DDDDDDDDD SSSSSSSSS OR D,S/# log CZMS 0101011 CZI CCCC DDDDDDDDD SSSSSSSSS XOR D,S/# log CZMS 0101100 CZI CCCC DDDDDDDDD SSSSSSSSS MUXC D,S/# log CZMS 0101101 CZI CCCC DDDDDDDDD SSSSSSSSS MUXNC D,S/# log CZMS 0101110 CZI CCCC DDDDDDDDD SSSSSSSSS MUXZ D,S/# log CZMS 0101111 CZI CCCC DDDDDDDDD SSSSSSSSS MUXNZ D,S/# log CZWS 0110000 CZI CCCC DDDDDDDDD SSSSSSSSS MOV D,S/# inc CZWS 0110001 CZI CCCC DDDDDDDDD SSSSSSSSS NOT D,S/# inc CZWS 0110010 CZI CCCC DDDDDDDDD SSSSSSSSS ABS D,S/# inc CZWS 0110011 CZI CCCC DDDDDDDDD SSSSSSSSS NEG D,S/# inc CZWS 0110100 CZI CCCC DDDDDDDDD SSSSSSSSS NEGC D,S/# inc CZWS 0110101 CZI CCCC DDDDDDDDD SSSSSSSSS NEGNC D,S/# inc CZWS 0110110 CZI CCCC DDDDDDDDD SSSSSSSSS NEGZ D,S/# inc CZWS 0110111 CZI CCCC DDDDDDDDD SSSSSSSSS NEGNZ D,S/# inc CZMS 0111000 CZI CCCC DDDDDDDDD SSSSSSSSS ALTDS D,S/# inc (modify D/S fields in D, redirect D/S fields in next instruction) CZWS 0111001 CZI CCCC DDDDDDDDD SSSSSSSSS DECOD D,S/# inc CZWS 0111010 CZI CCCC DDDDDDDDD SSSSSSSSS TOPONE D,S/# inc (find first '1' from MSB) CZWS 0111011 CZI CCCC DDDDDDDDD SSSSSSSSS BOTONE D,S/# inc (find first '1' from LSB) CZMS 0111100 CZI CCCC DDDDDDDDD SSSSSSSSS INCMOD D,S/# inc CZMS 0111101 CZI CCCC DDDDDDDDD SSSSSSSSS DECMOD D,S/# inc CZMS 0111110 CZI CCCC DDDDDDDDD SSSSSSSSS MUL D,S/# mul (16 x 16 unsigned multiply) CZMS 0111111 CZI CCCC DDDDDDDDD SSSSSSSSS MULS D,S/# mul (16 x 16 signed multiply) --MS 100000n nnI CCCC DDDDDDDDD SSSSSSSSS SETNIBn D,S/# mux --WS 100001n nnI CCCC DDDDDDDDD SSSSSSSSS GETNIBn D,S/# mux --MS 100010n nnI CCCC DDDDDDDDD SSSSSSSSS ROLNIBn D,S/# mux --MS 1000110 nnI CCCC DDDDDDDDD SSSSSSSSS SETBYTn D,S/# mux --WS 1000111 nnI CCCC DDDDDDDDD SSSSSSSSS GETBYTn D,S/# mux --MS 1001000 nnI CCCC DDDDDDDDD SSSSSSSSS ROLBYTn D,S/# mux --MS 1001001 0nI CCCC DDDDDDDDD SSSSSSSSS SETWRDn D,S/# mux --WS 1001001 1nI CCCC DDDDDDDDD SSSSSSSSS GETWRDn D,S/# mux --MS 1001010 0nI CCCC DDDDDDDDD SSSSSSSSS ROLWRDn D,S/# mux --WS 1001010 10I CCCC DDDDDDDDD SSSSSSSSS SETBYTS D,S/# mux --MS 1001010 11I CCCC DDDDDDDDD SSSSSSSSS MOVBYTS D,S/# mux --WS 1001011 00I CCCC DDDDDDDDD SSSSSSSSS SPLITB D,S/# mux --WS 1001011 01I CCCC DDDDDDDDD SSSSSSSSS MERGEB D,S/# mux --WS 1001011 10I CCCC DDDDDDDDD SSSSSSSSS SPLITW D,S/# mux --WS 1001011 11I CCCC DDDDDDDDD SSSSSSSSS MERGEW D,S/# mux --MS 1001100 00I CCCC DDDDDDDDD SSSSSSSSS SETS D,S/# mux --WS 1001100 01I CCCC DDDDDDDDD SSSSSSSSS GETS D,S/# mux --MS 1001100 10I CCCC DDDDDDDDD SSSSSSSSS SETD D,S/# mux --WS 1001100 11I CCCC DDDDDDDDD SSSSSSSSS GETD D,S/# mux --MS 1001101 00I CCCC DDDDDDDDD SSSSSSSSS SETDS D,S/# mux --MS 1001101 01I CCCC DDDDDDDDD SSSSSSSSS SETCOND D,S/# mux --MS 1001101 10I CCCC DDDDDDDDD SSSSSSSSS SETI D,S/# mux --WS 1001101 11I CCCC DDDDDDDDD SSSSSSSSS REV D,S/# mux --MS 1001110 00I CCCC DDDDDDDDD SSSSSSSSS DJZ D,S/@ inc/adr --MS 1001110 01I CCCC DDDDDDDDD SSSSSSSSS DJNZ D,S/@ inc/adr --MS 1001110 10I CCCC DDDDDDDDD SSSSSSSSS DJS D,S/@ inc/adr --MS 1001110 11I CCCC DDDDDDDDD SSSSSSSSS DJNS D,S/@ inc/adr --RS 1001111 00I CCCC DDDDDDDDD SSSSSSSSS TJZ D,S/@ adr --RS 1001111 01I CCCC DDDDDDDDD SSSSSSSSS TJNZ D,S/@ adr --RS 1001111 10I CCCC DDDDDDDDD SSSSSSSSS TJS D,S/@ adr --RS 1001111 11I CCCC DDDDDDDDD SSSSSSSSS TJNS D,S/@ adr CZRS 1010000 CZI CCCC DDDDDDDDD SSSSSSSSS TESTN D,S/# log (ANDN without write) CZRS 1010001 CZI CCCC DDDDDDDDD SSSSSSSSS TEST D,S/# log (AND without write) CZRS 1010010 CZI CCCC DDDDDDDDD SSSSSSSSS ANYB D,S/# log (OR without write) CZRS 1010011 CZI CCCC DDDDDDDDD SSSSSSSSS TESTB D,S/# log (ISOB without write) CZMS 1010100 CZI CCCC DDDDDDDDD SSSSSSSSS WAITCNT D,S/# add CZWS 1010101 CZI CCCC DDDDDDDDD SSSSSSSSS LINK D,S/@ adr (jump to S/@, write {C,Z,P[19:0]} to D, 'LINK INA,S/@' = 'JMP S/@') CZWS 1010110 CZI CCCC DDDDDDDDD SSSSSSSSS RDLUT D,S/# CZWS 1010111 CZI CCCC DDDDDDDDD SSSSSSSSS MSGIN D,S/# (receive pin S/# message into D) CZWS 1011000 CZI CCCC DDDDDDDDD SSSSSSSSS RDBYTE D,S/PTRx mem (waits for mem) CZWS 1011001 CZI CCCC DDDDDDDDD SSSSSSSSS RDWORD D,S/PTRx mem (waits for mem) CZWS 1011010 CZI CCCC DDDDDDDDD SSSSSSSSS RDLONG D,S/PTRx mem (waits for mem) ---- 1011011 --- ---- --------- --------- ---- 1011100 --- ---- --------- --------- --LS 1011101 0LI CCCC DDDDDDDDD SSSSSSSSS WRLUT D/#,S/# --LS 1011101 1LI CCCC DDDDDDDDD SSSSSSSSS MSGOUT D/#,S/# (send D/# message to pin S/#) --LS 1011110 0LI CCCC DDDDDDDDD SSSSSSSSS SETPAE D/#,S/# (sets INA '==' pattern) --LS 1011110 1LI CCCC DDDDDDDDD SSSSSSSSS SETPAN D/#,S/# (sets INA '!=' pattern) --LS 1011111 0LI CCCC DDDDDDDDD SSSSSSSSS SETPBE D/#,S/# (sets INB '==' pattern) --LS 1011111 1LI CCCC DDDDDDDDD SSSSSSSSS SETPBN D/#,S/# (sets INB '!=' pattern) --LS 1100000 0LI CCCC DDDDDDDDD SSSSSSSSS JP D/#,S/@ adr (jump if pin D/# high) --LS 1100000 1LI CCCC DDDDDDDDD SSSSSSSSS JNP D/#,S/@ adr (jump if pin D/# low) --LS 1100001 0LI CCCC DDDDDDDDD SSSSSSSSS WRBYTE D/#,S/PTRx mem (waits for mem) --LS 1100001 1LI CCCC DDDDDDDDD SSSSSSSSS WRWORD D/#,S/PTRx mem (waits for mem) --LS 1100010 0LI CCCC DDDDDDDDD SSSSSSSSS WRLONG D/#,S/PTRx mem (waits for mem) --LS 1100010 1LI CCCC DDDDDDDDD SSSSSSSSS RDLONGS D/#,S/# mem (read longs, D:rrrrrrrrr_nnnnnnnnn, S[19:0]:address) --LS 1100011 0LI CCCC DDDDDDDDD SSSSSSSSS WRLONGS D/#,S/# mem (write longs, D:rrrrrrrrr_nnnnnnnnn, S[19:0]:address) --LS 1100011 1LI CCCC DDDDDDDDD SSSSSSSSS RDFAST D/#,S/# mem (waits for mem, start fast read) --LS 1100100 0LI CCCC DDDDDDDDD SSSSSSSSS WRFAST D/#,S/# mem (waits for mem, start fast write) --LS 1100100 1LI CCCC DDDDDDDDD SSSSSSSSS FBLOCK D/#,S/# mem (update RDFAST/WRFAST size,start) --LS 1100101 0LI CCCC DDDDDDDDD SSSSSSSSS XINIT D/#,S/# (transfer init, reset phase) --LS 1100101 1LI CCCC DDDDDDDDD SSSSSSSSS XZERO D/#,S/# (transfer update, wait for rollover, reset phase) --LS 1100110 0LI CCCC DDDDDDDDD SSSSSSSSS XCONT D/#,S/# (transfer update, wait for rollover, continue) --LS 1100110 1LI CCCC DDDDDDDDD SSSSSSSSS REP D/#,S/# (begin repeat block of size D/# with S/# iterations) C-LS wr if !L 1100111 CLI CCCC DDDDDDDDD SSSSSSSSS COGINIT D/#,S/# 2 (0010) wait sys + 2 if WC and reg --LS 1101000 0LI CCCC DDDDDDDDD SSSSSSSSS QMUL D/#,S/# 2 (1000) wait sys --LS 1101000 1LI CCCC DDDDDDDDD SSSSSSSSS QDIV D/#,S/# 3 (1001) wait sys --LS 1101001 0LI CCCC DDDDDDDDD SSSSSSSSS QSQR D/#,S/# 2 (1010) wait sys --LS 1101001 1LI CCCC DDDDDDDDD SSSSSSSSS QSIN D/#,S/# 2 (1011) wait sys --LS 1101010 0LI CCCC DDDDDDDDD SSSSSSSSS QROT D/#,S/# 2 (1100) wait sys --LS 1101010 1LI CCCC DDDDDDDDD SSSSSSSSS QATN D/#,S/# 3 (1101) wait sys CZL- wr if C 1101011 CZL CCCC DDDDDDDDD 000000000 CLKSET D/# 1 0 (0000) wait sys + 2 if WC/WZ (result in D) CZL- wr if !C!L 1101011 CZL CCCC DDDDDDDDD 000000001 COGID D/# WC 1 0/C (0001) wait sys + 2 CZL- 1101011 00L CCCC DDDDDDDDD 000000011 COGSTOP D/# 1 0 (0011) wait sys CZL- wr 1101011 CZ0 CCCC DDDDDDDDD 000000100 LOCKNEW D 0 1/C (0100) wait sys + 2 CZL- 1101011 00L CCCC DDDDDDDDD 000000101 LOCKRET D/# 1 0 (0101) wait sys CZL- 1101011 C0L CCCC DDDDDDDDD 000000110 LOCKCLR D/# 1 0/C (0110) wait sys + 2 if WC CZL- 1101011 C0L CCCC DDDDDDDDD 000000111 LOCKSET D/# 1 0/C (0111) wait sys + 2 if WC CZL- 1101011 00L CCCC DDDDDDDDD 000001110 QLOG D/# 1 (1110) wait sys CZL- 1101011 00L CCCC DDDDDDDDD 000001111 QEXP D/# 1 (1111) wait sys CZL- wr 1101011 CZ0 CCCC DDDDDDDDD 000010000 RFBYTE D CZL- wr 1101011 CZ0 CCCC DDDDDDDDD 000010001 RFWORD D CZL- wr 1101011 CZ0 CCCC DDDDDDDDD 000010010 RFLONG D CZL- 1101011 00L CCCC DDDDDDDDD 000010011 WFBYTE D/# CZL- 1101011 00L CCCC DDDDDDDDD 000010100 WFWORD D/# CZL- 1101011 00L CCCC DDDDDDDDD 000010101 WFLONG D/# CZL- 1101011 00L CCCC DDDDDDDDD 000010110 WAITX D/# (wait 2 + D/# clocks) CZL- 1101011 00L CCCC DDDDDDDDD 000010111 SETQ D/# CZL- wr 1101011 CZ0 CCCC DDDDDDDDD 000011000 GETQX D (wait for CORDIC result) CZL- wr 1101011 CZ0 CCCC DDDDDDDDD 000011001 GETQY D (wait for CORDIC result) CZL- wr 1101011 000 CCCC DDDDDDDDD 000011010 GETCNT D CZL- wr 1101011 CZ0 CCCC DDDDDDDDD 000011011 GETRND D/WC/WZ (get random value and/or bit) CZL- 1101011 00L CCCC DDDDDDDDD 000011100 SETXDAC D/# CZL- 1101011 00L CCCC DDDDDDDDD 000011101 SETXFRQ D/# CZL- wr 1101011 000 CCCC DDDDDDDDD 000011110 GETXCOS D (get transfer Goertzel X) CZL- wr 1101011 000 CCCC DDDDDDDDD 000011111 GETXSIN D (get transfer Goertzel Y) CZL- 1101011 00L CCCC DDDDDDDDD 000100000 SETPER D/# (set 32-bit period for recurring timer event) CZL- 1101011 00L CCCC DDDDDDDDD 000100001 SETEDG D/# (set 2-bit edge and 6-bit pin/lock number for edge event) CZL- 1101011 00L CCCC DDDDDDDDD 000100010 SETRDL D/# (set 4-bit index for universal RDLONG events) CZL- 1101011 00L CCCC DDDDDDDDD 000100011 SETWRL D/# (set 4-bit index for universal WRLONG events) CZL- 1101011 C00 CCCC 000000000 000100100 GETINT (get interrupt-event flag into C, clear flag) CZL- 1101011 C00 CCCC 000000001 000100100 GETPER (get timer-event flag into C, clear flag) CZL- 1101011 C00 CCCC 000000010 000100100 GETEDG (get edge-event flag into C, clear flag) CZL- 1101011 C00 CCCC 000000011 000100100 GETPAT (get pattern-event flag into C, clear flag) CZL- 1101011 C00 CCCC 000000100 000100100 GETRDL (get RDLONG-event flag into C, clear flag) CZL- 1101011 C00 CCCC 000000101 000100100 GETWRL (get WRLONG-event flag into C, clear flag) CZL- 1101011 C00 CCCC 000000110 000100100 GETXRO (get transfer-rollover-event flag into C, clear flag) CZL- 1101011 C00 CCCC 000000111 000100100 GETFBW (get fast-block-wrap-event flag into C, clear flag) CZL- 1101011 C00 CCCC 000001000 000100100 WAITINT (wait for interrupt event, WC=1 for timeout using Q) CZL- 1101011 C00 CCCC 000001001 000100100 WAITPER (wait for timer-event flag, clear flag, WC=1 for timeout using Q) CZL- 1101011 C00 CCCC 000001010 000100100 WAITEDG (wait for edge-event flag, clear flag, WC=1 for timeout using Q) CZL- 1101011 C00 CCCC 000001011 000100100 WAITPAT (wait for pattern-event flag, clear flag, WC=1 for timeout using Q) CZL- 1101011 C00 CCCC 000001100 000100100 WAITRDL (wait for RDLONG-event flag, clear flag, WC=1 for timeout using Q) CZL- 1101011 C00 CCCC 000001101 000100100 WAITWRL (wait for WRLONG-event flag, clear flag, WC=1 for timeout using Q) CZL- 1101011 C00 CCCC 000001110 000100100 WAITXRO (wait for transfer-rollover-event flag, clear flag, WC=1 for timeout using Q) CZL- 1101011 C00 CCCC 000001111 000100100 WAITFBW (wait for fast-block-wrap-event flag, clear flag, WC=1 for timeout using Q) CZL- 1101011 00L CCCC DDDDDDDDD 000100101 SETINT1 D/# (set 3-bit mode for interrupt 1) CZL- 1101011 00L CCCC DDDDDDDDD 000100110 SETINT2 D/# (set 3-bit mode for interrupt 2) CZL- 1101011 00L CCCC DDDDDDDDD 000100111 SETINT3 D/# (set 3-bit mode for interrupt 3) CZL- 1101011 00L CCCC DDDDDDDDD 000101000 PUSH D/# (push D[21:0] into 8-level stack) CZL- 1101011 CZ0 CCCC DDDDDDDDD 000101001 CALL D (call to D[19:0] using 8-level stack, D[21:20] into C,Z) CZL- 1101011 CZ0 CCCC DDDDDDDDD 000101010 CALLA D (call to D[19:0] using PTRA stack, D[21:20] into C,Z) CZL- 1101011 CZ0 CCCC DDDDDDDDD 000101011 CALLB D (call to D[19:0] using PTRB stack, D[21:20] into C,Z) CZL- wr 1101011 CZ0 CCCC DDDDDDDDD 000101100 POP D (pop 8-level stack into D, D[21:20] into C,Z) CZL- 1101011 CZ0 CCCC 000000000 000101101 RET (return using 8-level stack, STK[21:20] into C,Z) CZL- 1101011 CZ0 CCCC 000000000 000101110 RETA (return using PTRA stack, mem[21:20] into C,Z) CZL- 1101011 CZ0 CCCC 000000000 000101111 RETB (return using PTRB stack, mem[21:20] into C,Z) CZL- 1101011 000 CCCC 000000000 000110000 WFMASK (enable WFxxxx masking, skip writing $FF-value bytes) CZL- 1101011 000 CCCC 000000000 000110001 WFNORM (disable WFxxxx masking - default) CZL- 1101011 000 CCCC 000000000 000110010 STALLI (stall interrupts) CZL- 1101011 000 CCCC 000000000 000110011 ALLOWI (allow interrupts - default) CZL- 1101011 000 CCCC 000000000 000110100 SETBRK D/# (set debug breakpoint) ---- 1101100 Rnn CCCC nnnnnnnnn nnnnnnnnn JMP #abs/@rel (jump to 20-bit absolute/relative address) ---- 1101101 Rnn CCCC nnnnnnnnn nnnnnnnnn CALL #abs/@rel (call to 20-bit absolute/relative address, using 8-level stack) ---- 1101110 Rnn CCCC nnnnnnnnn nnnnnnnnn CALLA #abs/@rel (call to 20-bit absolute/relative address using PTRA) ---- 1101111 Rnn CCCC nnnnnnnnn nnnnnnnnn CALLB #abs/@rel (call to 20-bit absolute/relative address using PTRB) ---- wr 11100ww Rnn CCCC nnnnnnnnn nnnnnnnnn LINK reg,#abs/@rel (jump to 20-bit absolute/relative address, write {C,Z,P[19:0]} to $1F6..$1F9) ---- wr 11101ww Rnn CCCC nnnnnnnnn nnnnnnnnn LOC reg,#abs/@rel (write 20-bit absolute/relative address to $1F6..$1F9, includes PTRA/PTRB) ---- 11110nn nnn CCCC nnnnnnnnn nnnnnnnnn AUGS #23bits (appends n to upper bits of next immediate S) ---- 11111nn nnn CCCC nnnnnnnnn nnnnnnnnn AUGD #23bits (appends n to upper bits of next immediate D) Aliases for WRLONG/RDLONG: PUSHA/PUSHB/POPA/POPB C effect ------------------------------------------------------------------------------------------ 0 1 wc Z effect ------------------------------------------------------------------------------------------ 0 1 wz I SSSSSSSSS source operand ------------------------------------------------------------------------------------------ 0/na SSSSSSSSS register 1 #SSSSSSSSS immediate, zero-extended L DDDDDDDDD destination operand ------------------------------------------------------------------------------------------ 0/na DDDDDDDDD register 1 #DDDDDDDDD immediate, zero-extended CCCC condition (easier-to-read list) ------------------------------------------------------------------------------------------ 0000 never 1111 if_always (default) 0001 nc & nz 1100 if_c if_b if_x1 0010 nc & z 0011 if_nc if_ae if_x0 0011 nc 1010 if_z if_e if_1x 0100 c & nz 0101 if_nz if_ne if_0x 0101 nz 1000 if_c_and_z if_z_and_c if_11 0110 c <> z 0100 if_c_and_nz if_nz_and_c if_01 0111 nc | nz 0010 if_nc_and_z if_z_and_nc if_10 1000 c & z 0001 if_nc_and_nz if_nz_and_nc if_a if_00 1001 c = z 1110 if_c_or_z if_z_or_c if_be if_not_00 1010 z 1101 if_c_or_nz if_nz_or_c if_not_10 1011 nc | z 1011 if_nc_or_z if_z_or_nc if_not_01 1100 c 0111 if_nc_or_nz if_nz_or_nc if_not_11 1101 c | nz 1001 if_c_eq_z if_z_eq_c if_same 1110 c | z 0110 if_c_ne_z if_z_ne_c if_diff 1111 always 0000 if_never SETEDG %L_EE_PPPPPP ---------------------------------------------------------- %L: 0 = pin 1 = lock %EE: 00 = any edge %EE: 01 = pos edge %EE: 10 = neg edge %EE: 11 = any edge %PPPPPP: pin number %xxPPPP: lock number SETRDL %RRRR ---------------------------------------------------------- %RRRR: RDLONG-event address %0000_0000_0000_00RR_RR00 SETWRL %WWWW ---------------------------------------------------------- %WWWW: WRLONG-event address %0000_0000_0000_00WW_WW00 SETINT1/SETINT2/SETINT3 %MMM ---------------------------------------------------------- %MMM: 000 = disable interrupt - default 001 = enable timer-event interrupt 010 = enable edge-event interrupt 011 = enable RDLONG-event interrupt 100 = enable WRLONG-event interrupt 101 = enable transfer-rollover-event interrupt 110 = enable fast-block-wrap-event interrupt