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Thread: Hydra "xtreme 512k card" sram status

  1. #1

    Default Hydra "xtreme 512k card" sram status

    Ok, got the HYDRA sram cards back, built one, worked 100% first try. All the modes seems to work, post inc, dec, latching, etc. Been trying to cause noise problems to see if ever there is a lost bit, none yet. Now, I am going to start running some final high speed tests, and if all works out then start on the documentation and final product stuff and send it to manufacturing for bulk production. While that goes on we will work on some graphics driver demos, but we want to release this asap, so software will not delay release, once the hardware is ready to ship, we will put it for sale.

    But, looks good so far, LOTS of LEDs on it :) And once again for those not following this, the features are:

    - 128K EEPROM on board.
    - 512K SRAM.
    - 0-64K directly addressable by latching 2 byte address.
    - 64-512K addressable by block addressing and pointer incrementing/decrementing in the memory controller.

    - Re-Programmable CPLD

    Target price $39-49

    Cool thing, can be used with anything... just need a 20-pin edge connector 10/10 with .1" spacing and you can plug it in. So you can add it to other propeller or stamp projects as well.

    You need 3 (control) + 8· (data) lines to interface.

    Andre'
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    Last edited by ForumTools; 09-30-2010 at 01:53 AM. Reason: Forum Migration

  2. #2

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    Can't wait to get my hands on it : D ...

    But 3+8 lines... that means you're using all the I/O lines, both HydraNet lines but where does the third control line come from? SCL? And there prolly isn't a CS line, so a SD card can't be added... as 3 ctrl lines are just enough for R/W, clock and a mode setting/address loading ctrl...

    And can the CPLD be programmed with free tools? Free tools that work with a self-built serial or parallel cable?
    Last edited by ForumTools; 09-30-2010 at 01:53 AM. Reason: Forum Migration

  3. #3

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    I am using the RX line for the 3rd. And yes, the CPLD can be re-programmed with free tools in ABEL. And I will provide the schematic for the programmer, very simple actually with the parallel port.

    Right now I am running fractal rendering algorithms in the SRAM and scrolling them around to test the memory with something graphical, much easier to "see" bugs that with all the standard tests marching 1's, 0's, patterns, blah, blah. All that works, so now doing lots of graphics in the memory. Then next will be the graphics driver that uses it and see how fast I can push it all. Of course the CPLD goes much faster than the prop, 200-400 Mhz roughly.

    Andre'
    Last edited by ForumTools; 09-30-2010 at 01:53 AM. Reason: Forum Migration

  4. #4

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    Sorry for sounding ignorent but what is a CLPD?

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    lets see what this does... KA BOOM (note to self do not cross red and black)
    Last edited by ForumTools; 09-30-2010 at 01:53 AM. Reason: Forum Migration

  5. #5

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    Complex Programmable Logic Device

    Basically, a 2D matrix of "logic blocks" connected together with a switching matrix. Each block usually consists of a flip flip, mux, IO, look up table, and some simple or/and logic.

    You write code in a HDL (Hardware Description language) and this is translated into the target CPLDs architecture and "fit" into it then the resulting "program" is downloaded into the CPLD and this configures it for use.

    The FPGAs are the next size up, "field programmable gate array" which is really a bad name. I think VCPLD would be better, that is, VERY complex programmable logic device.

    hmmm...I think I will patent that!

    Andre'
    Last edited by ForumTools; 09-30-2010 at 01:53 AM. Reason: Forum Migration

  6. #6

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    Ah, all the time I've thought that the RX/TX pins are connected to the USB end of the FTDI chip, not the serial end (well, that wouldn't have made any sense... since USB needs 4 pins and it'd be of very little use anyway...). So with sharing some pins w/ the EEPROM and SRAM, it might be still possible to add SD support ... Does the card have 0,1" holes for signals like the other cards?

    Oh and by the way, what'd be my chances of breaking the I2C chip on the card if i'd cut the address pin, solder it to +3,3V and cut the loop lines? a) Would it work, ie. would I have 256KB of EEPROM after that b) would I break the I2C chip with heat if I'd try to solder a pin that has been cut?
    Last edited by ForumTools; 09-30-2010 at 01:53 AM. Reason: Forum Migration

  7. #7

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    The EEPROM is totally seperate, so you can cut lines or remove it if you want. Cutting the loop might prove a little harder since I used a lot of copper, but a knife and a steady hand, no problem. As far as header holes no luck, "but" all of the header pins used are via'd to the other side of the board, so you can squirel wires into them if you want to.

    Andre'
    Last edited by ForumTools; 09-30-2010 at 01:53 AM. Reason: Forum Migration

  8. #8

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    Okay, thanks André. : ) ... And if I can't find a way to solder anything to the Xtreme card without damaging it permanently, I might solder the wires directly to the extension socket pins under the Hydra. And I'm prolly trying to mod the GameCard that came w/ the Hydra today or tomorrow to work as an EEPROM extension to get 2 cascaded EEPROM chips.
    Last edited by ForumTools; 09-30-2010 at 01:53 AM. Reason: Forum Migration

  9. #9

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    Also, FYI, the eeproms already do cascade. When you plug in the expansion card, it selects the card eeprom at address 0, then teh board eeprom becomes address 1, so a total of 256K is available.

    Andre'
    Last edited by ForumTools; 09-30-2010 at 01:53 AM. Reason: Forum Migration

  10. #10

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    Okay... O_O I was nearly gonna ruin my EEPROM card :D thank you very much... Yes, I know that it is in the book, I have no idea why I didn't notice it : P
    Last edited by ForumTools; 09-30-2010 at 01:53 AM. Reason: Forum Migration

  11. #11

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    Also, the blank experimenter card is a good place to start as well. The parallax mini white solderless breadboard fits on it and you can use that plus the header to interace experiments before commiting them to solder.

    Andre'
    Last edited by ForumTools; 09-30-2010 at 01:53 AM. Reason: Forum Migration

  12. #12

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    Thank you Andrel for the explanation of a CLPD

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    lets see what this does... KA BOOM (note to self do not cross red and black)
    Last edited by ForumTools; 09-30-2010 at 01:53 AM. Reason: Forum Migration

  13. #13

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    Sure. Also, we are going to release a "Programmable Logic Starter Kit" soon that features a CPLD, built in programmer, tutorials, and all for under $99. Basically, to get people into CPLDs and FPGAs that don't know where to start.

    Andre'
    Last edited by ForumTools; 09-30-2010 at 01:53 AM. Reason: Forum Migration

  14. #14

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    Sounds good ^_^ And I'm going to prototype on a breadboard anyway, that's what I always do...

    You said that the CPLD can be programmed with ABEL. I've never heard of that language before, why isn't it programmed with Verilog or VHDL? Or can they be used as well?
    Last edited by ForumTools; 09-30-2010 at 01:53 AM. Reason: Forum Migration

  15. #15

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    verilog/vhdl are higher level and more abstract. Higher abstraction means less control, less control means more assumptions for the silicon compiler, so for smaller CPLDs ABLE or CUPL are preferred. You can look them both up to get an idea of the syntax, but similar to verilog, not as powerful, but much more specific.

    Andre'
    Last edited by ForumTools; 09-30-2010 at 01:53 AM. Reason: Forum Migration

  16. #16

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    Ok, so Verilog & VHDL usually generate code that's far too inefficient for CPLDs? ... I'll take a look at CUPL and ABEL etc. when I have the card and a programming cable : P

    And is the difference between an FPGA & CPLD only a quantitative one? Or is there a difference between the functionality of logic blocks or routing?
    Last edited by ForumTools; 09-30-2010 at 01:53 AM. Reason: Forum Migration

  17. #17

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    Whether Verilog/VHDL can be used with CPLDs depends on the number of cells and the project. There is a structural difference between CPLDs and FPGAs, I suggest checking out the specsheets for various devices so you will fully understand. FPGAs in general are much more configurable than CPLDs, it is the extra confurability and less dependance on·optimized layout that enables semi-automated programs such as Verilog to work well. It's relative inability to optimize placement of logic equations in a confined configuration of a CPLD as compared to a human is what makes using a lower level program such as ABEL a better choice.

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    Paul Baker
    Propeller Applications Engineer

    Parallax, Inc.

    Post Edited (Paul Baker (Parallax)) : 3/18/2007 3:50:57 PM GMT
    Last edited by ForumTools; 09-30-2010 at 01:53 AM. Reason: Forum Migration

  18. #18

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    Wow, thanks for your replies André & Paul ^__^ I'll take a look at some datasheets or something...
    Last edited by ForumTools; 09-30-2010 at 01:53 AM. Reason: Forum Migration

  19. #19

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    People have even written translators from C, python, and other languages to verilog as well, so the main point about HDL programming is just understanding parallel programming, the language is really just syntax that you have to memorize and you spent 99% of your time trying to figure out the syntax of how to say what you want to say.

    Andre'
    Last edited by ForumTools; 09-30-2010 at 01:53 AM. Reason: Forum Migration

  20. #20

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    What sort of projects are you looking at doing with the "Programmable logic starter kit" andre'?? Anything as complex as a GPU or a very simple CPU? Something that like a GPU that could be used in combination with the Hydra would be very cool
    Last edited by ForumTools; 09-30-2010 at 01:53 AM. Reason: Forum Migration

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