Search:

Type: Posts; User: jac_goudsmit

Page 1 of 8 1 2 3 4

Search: Search took 0.01 seconds.

  1. Re: New P1V capabilities added - a COGRAM stack

    Added to the Github TODO list!

    ===Jac
  2. Re: NEW! Fast indirect access to COG RAM with LOAD/STORE instructions

    This is a great feature! I'll add it to my TO DO list of things to add to Github.

    ===Jac
  3. Replies
    16
    Views
    752

    Re: Added COGS define.

    You should set up separate stacks for each cog, instead of one stack for all cogs.

    Also, I seem to remember that there's a problem with just putting "repeat" in the code without a body (I think...
  4. Replies
    16
    Views
    810

    Re: Replacing AHDL with VHDL

    Ah, sorry. I tried to find you on Github and didn't see you, so I went ahead and checked the Verilog conversion into my Altera branch, crediting you and Magnus. That was before I saw the PLL fix,...
  5. Replies
    16
    Views
    810

    Re: Replacing AHDL with VHDL

    Seairth, are you on Github? If not, do you mind if I check in your changes (giving you full credit of course)?

    By the way, I think in tim.v, reg[7:0] cfgx should be reg[6:0] cfgx (it gets copied...
  6. Re: Getting organized, part 3: TO DO list on Github

    Thanks!



    That's correct.

    The Altera branch has the reorganized source code where all Altera targets share the same project file and source files. The Xilinx branch will have the combined...
  7. Replies
    7
    Views
    206

    Re: Did I find a bug in cog_ctr.v?

    Good find, Andy! I looked at the code and I'm pretty sure that yes, this is a bug.

    I fixed the bug in my Master and Altera branches (the two main branches I'm working in), and updated my...
  8. Re: Getting organized, part 3: TO DO list on Github

    Thanks Brian and Ray!

    I updated the first post and the Wiki page.

    ===Jac
  9. Re: Getting organized, part 3: TO DO list on Github

    Thanks!



    I used the Spin program that you published earlier to generate the ROM image hex files from the original P1V. My modified version (currently only on my PC at home) creates one 32-bit...
  10. Getting organized, part 3: TO DO list on Github

    Hi all!

    I've been working on a change to the hub_mem.v module to make it possible to easily change the sizes of the RAM and ROM in the hub (as hardware allows). As I may have mentioned, I want to...
  11. Replies
    7
    Views
    382

    Re: Run P1v under emulation?

    Quartus has a simulator and a logic analyzer built in but I don't know how it works (yet). I'm going to have to look into it though, because as you say, testing on the FPGA is not easy, especially if...
  12. Re: New PUSH and POP functionality added for single hub cycle LMM and other hub trans

    Rogloh, I'm interested in integrating this feature into the Github repo (it may take a few days before I get to it, ideas are stacking up in my virtual "inbox").

    If you have a Github account, can...
  13. Replies
    15
    Views
    689

    Re: Cyclone V GX Starter Kit

    Would you care to share your source files? I'll put them up on Github. I may order one of the two boards discussed here when they become available; the BeMicro is nice but I don't have anything to...
  14. Re: ROM files (unscrambled) and verilog changes for increased Hub RAM

    Thanks Ray!

    I already started merging that code into my Cluso99 branch and I already added a parameter too, except I named it something else (parameter CLUSO99_HUBRAM_SIZE_LONGS = 8192 or...
  15. Replies
    15
    Views
    689

    Re: Cyclone V GX Starter Kit

    @Cluso99: It has a 20x2 header and (partially shared) Arduino headers for I/O. That's enough for my purposes. Looks like the HDMI is not usable without an additional IP license, though (not...
  16. Replies
    15
    Views
    689

    Cyclone V GX Starter Kit

    I just noticed that Altera/Terasic sells a Cyclone V GX starter kit for $179 but it's out of stock right now.

    The capabilities of this board and this FPGA are somewhat between the DE0 and the DE2;...
  17. Re: Propeller 1 running on Pipistrello (Xilinx Spartan6-LX45)

    I'll probably integrate this into Github later today. It needs a few small changes because your version has tabs (not spaces) and you started from a version of Magnus' code that he reverted. Thanks...
  18. Re: MiST (uses Cyclone III) board with P1V?

    The Cyclone V on the BeMicroCV has fewer than (the equivalent of) 10,000 LE's and it fits there, but it has lots of RAM as well. If the EP3C25 has enough RAM, or if Quartus can figure out how to use...
  19. Re: MiST (uses Cyclone III) board with P1V?

    That's an interesting board! I've looked at the Minimig in the past too, before Parallax got me interested in FPGAs.

    I'm not an FPGA expert, but I have a pretty good idea what's in an Amiga 500 or...
  20. Re: Simple regression suite to test FPGA vs P8X32A

    Heater: Thanks for the update. I hope Parallax will join us on Github soon. You can pull my master branch at any time (you shouldn't need a pull request I think), I'm not planning on making any major...
  21. Replies
    16
    Views
    810

    Re: Replacing AHDL with VHDL

    I agree with Seairth, it would be better to have a tim.v to replace the original and to keep the modules organized in the same way as the original files so that new users can easily observe how the...
  22. Replies
    6
    Views
    880

    Re: LCD working on FPGA-board!

    I don't have a Xilinx board and I've never even seen the Xilinx software (I have about two weeks more experience with Quartus haha), but maybe it's possible to combine your Spartan-3E build with...
  23. Re: Getting organized, part 2: Quartus Revisions, Preprocessor Macros and Parameters

    If you simply want to download the files without setting up Github, you can simply go to my Altera branch page and click the "Download Zip" button on the right, even if you don't have a Github...
  24. Replies
    6
    Views
    880

    Re: LCD working on FPGA-board!

    Nice! Do you have any plans to add your code to Github?

    ===Jac
  25. Re: Simple regression suite to test FPGA vs P8X32A

    I would be very interested in this.

    I just reorganized the Github repo that Heater started and Mindrobots expanded, so that it only contains one tree of files for the Altera targets (I'm a...
Results 1 to 25 of 197
Page 1 of 8 1 2 3 4