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Type: Posts; User: jac_goudsmit

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  1. Re: Port B and Counters, Video Generators and FSRW

    Great stuff, 6581!

    I see you cloned my Github repo, so it should be easy to pull your changes back in, once I figure out how to do that :-)

    I'm reviewing your changes now, the only minor...
  2. Re: BeMicro Max10 initial tests: 3 cogs wil fit.

    I think smart compilation is turned on (at least for the BeMicroCV revision in my project). When you click the build button and nothing has changed to the source code, it won't actually build. But...
  3. Re: BeMicro Max10 initial tests: 3 cogs wil fit.

    I added the numbers in the last row. It's not a fair comparison because the LE's in each device work slightly different, and the P1V project could probably use some optimization. I think I actually...
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    Re: BeMicro CV A9 - 301.000K LE

    I agree, but I think that's unlikely to happen: The A9 FPGA contains an ARM core, and Altera probably has to pay license fees to ARM to integrate the compiler in their Quartus tool so they can't...
  5. BeMicro Max10 initial tests: 3 cogs wil fit.

    6581 posted a message about the BeMicro A9 which is probably out of range for most of us.

    The BeMicro Max10 is going to be $30 (it's not available yet), so it's going to be in range of more...
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    Re: BeMicro CV A9 - 301.000K LE

    Also, keep in mind that the free version of Quartus doesn't support the A9, you have to get the paid version.

    I think for most of us the A9 is out of our league...

    ===Jac
  7. Re: Expanding the P1V's instruction set (A Poor mans P2)

    I don't think the if_never instructions are a good place to put new instructions. I only have one major project with a Propeller and it uses a MUX instruction to change the conditional bits between...
  8. Re: BeMicroCV EEPROM Modification, Peripheral Pin Selection

    I think it should be possible to make future alternate bootloaders possible by checking P28/P29 for the usual 100k pullup resistors. If they're there, the boot loader can start from EEPROM, otherwise...
  9. Re: BeMicroCV EEPROM Modification, Peripheral Pin Selection

    This is a great idea, and I was thinking of doing the same. However I don't have an SMD version of a 24LC512 so I haven't gotten to it yet. Maybe I'll dead-bug a PDIP EEPROM on the top side (TP7 and...
  10. Re: Idea: Propeddle with the P1V and a 6502 Softcore

    I apologize if my remark was interpreted that way; I didn't intend to be rude.

    Using the on-board SD card reader on the BeMicro CV and other boards would be extremely useful and would be something...
  11. Re: Idea: Propeddle with the P1V and a 6502 Softcore

    I fail to see how the previous 3 posts fit in this thread...

    ===Jac
  12. Re: Idea: Propeddle with the P1V and a 6502 Softcore

    Of course I've thought about this but let's think about this for a minute.

    First of all, with the P1V code, the Cyclone 5 that's on the BeMicro CV is almost full. Adding a soft-core 6502 to the...
  13. Poll: Re: Suggestion: Putting P1V Code on GitHub / Shared Code Repo.

    I don't know what you mean with "split repositories under a tag".

    One of the most important benefits of Github is that efforts of multiple people can be combined: If many developers all post zip...
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    Re: Getting organized, part 3: TO DO list on Github

    I updated the top post to the latest status. Is there any way we can make this a Sticky?

    ===Jac
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    Re: Understanding timing analysis

    I haven't been able to work on the code since last week (work got a little busy) but I'm putting the timing analysis and the idea of shared video on the to-do list. (Sorry for bumping the thread).
    ...
  16. Re: New P1V capabilities added - a COGRAM stack

    Added to the Github TODO list!

    ===Jac
  17. Re: NEW! Fast indirect access to COG RAM with LOAD/STORE instructions

    This is a great feature! I'll add it to my TO DO list of things to add to Github.

    ===Jac
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    Re: Added COGS define.

    You should set up separate stacks for each cog, instead of one stack for all cogs.

    Also, I seem to remember that there's a problem with just putting "repeat" in the code without a body (I think...
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    Re: Replacing AHDL with VHDL

    Ah, sorry. I tried to find you on Github and didn't see you, so I went ahead and checked the Verilog conversion into my Altera branch, crediting you and Magnus. That was before I saw the PLL fix,...
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    Re: Replacing AHDL with VHDL

    Seairth, are you on Github? If not, do you mind if I check in your changes (giving you full credit of course)?

    By the way, I think in tim.v, reg[7:0] cfgx should be reg[6:0] cfgx (it gets copied...
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    Re: Getting organized, part 3: TO DO list on Github

    Thanks!



    That's correct.

    The Altera branch has the reorganized source code where all Altera targets share the same project file and source files. The Xilinx branch will have the combined...
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    Re: Did I find a bug in cog_ctr.v?

    Good find, Andy! I looked at the code and I'm pretty sure that yes, this is a bug.

    I fixed the bug in my Master and Altera branches (the two main branches I'm working in), and updated my...
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    Re: Getting organized, part 3: TO DO list on Github

    Thanks Brian and Ray!

    I updated the first post and the Wiki page.

    ===Jac
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    Re: Getting organized, part 3: TO DO list on Github

    Thanks!



    I used the Spin program that you published earlier to generate the ROM image hex files from the original P1V. My modified version (currently only on my PC at home) creates one 32-bit...
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    Github TO DO list

    Hi all!

    I've been working on a change to the hub_mem.v module to make it possible to easily change the sizes of the RAM and ROM in the hub (as hardware allows). As I may have mentioned, I want to...
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